WESTLAKE VILLAGE, Calif., 20 Jan 2009. Inphi Corp. in Westlake Village, Calif., is introducing a 28G bit error ratio (BER) receiver reference design for testing and researching emerging high-speed protocols from 13 to 28 gigabits per second, including 100 Gigabit Ethernet, 40G Differential Quadrature Phase Shift Keying (DQPSK), 14G Fibre Channel, and 100G Dual-Polarization Quadrature Phase Shift Keying (DP-QPSK).

For high-speed data links, BER testing is a fundamental test at the physical layer, as it measures whether the data bits are correctly transmitted across the link.

BERT systems for speeds as fast as 12.5 gigabits per second are well established, yet design and test engineers require BERTs with fast front-ends above 12.5 gigabits per second, as fast as 28 gigabits per second with the emergence of networking standards such as 40G SONET, 100G Ethernet, and 14G Fibre Channel.

The Inphi 28G BER receiver helps engineers design a high-speed front end at 28 gigabits per second, and integrates an Inphi chipset. The reference design, together with a 12.5G BERT and a 28G fast test pattern generator, comprise a 28-gigabit-per-second test solution.

For test applications requiring clock recovery, the 28G BER receiver reference design provides a buffered copy of the high-speed input data stream, which can be supplied to an optional clock recovery unit to generate a recovered clock. For more information contact Inphi online at www.inphi-corp.com.