All Access


Nallatech launches PCI Express 2.0 FPGA accelerator card

Posted by Courtney Howard

CAMARILLO, Calif., 10 May 2010. Nallatech, a supplier of high-performance COTS FPGA solutions, announced its PCIe-280, an 8-lane PCI Express 2.0 FPGA accelerator card. The PCIe-280, able to increase application performance by harnessing up to 5GByte/sec of sustained host bandwidth, is targeted at signal intelligence, network security, and algorithm acceleration applications.

The PCIe-280 features an onboard Xilinx Virtex-5 user FPGA directly coupled to a high-bandwidth, flexible memory configuration that includes ECC and parity protection. Two independent banks of QDR-II SRAM provide 8GBytes/sec of sustained, random access memory bandwidth. Up to two banks of DDR2 SDRAM memory provide 4GBytes/sec of deep storage local to the user FPGAs. Thirty-two high-speed serial I/O links are exposed at the top of the card, allowing multiple PCIe-280 cards to be interconnected via low-latency, point-to-point links.
 
“Market demand for FPGA-attached server and blade platforms is growing rapidly as customers begin to deploy hybrid computing platforms in greater volumes,” says Craig Petrie, product manager at Nallatech. “Sustained host bandwidth performance is a critical parameter for many customer applications.”
 
The PCIe-280 is compatible with high-density server and blade centre platforms from OEMs such as Cray, Dell, HP, IBM, SGI, and Supermicro. Optimized VHDL memory controller IP cores and reference designs are included as part of the standard product deliverables along with driver and API source code for 64-bit Linux operating systems. Onboard FPGA, memory, and I/O can be increased through population of compatible DIME-II modules.
 

Font Sizes:

Easily post a comment below using your Linkedin, Twitter, Google or Facebook account.


Most Popular Articles

Wire News provided by   

Webcasts

Upcoming

High Performance ADC & DAC Solutions with Reconfigurable DSP for Sense & Response Applications

This webinar will discuss recent developments in data converter and FPGA technology that are now available in a COTS, open standards platform, that sets a new bar in processing capability for high bandwidth,...
( 06/20/2013 / 10:00 AM Central Daylight Time / 11:00 AM Eastern Daylight Time / 08:00 AM Pacific Daylight Time / 15:00 GMT )

Thermal Design in Military Embedded Computing Applications

This webcast sponsored by Advanced Cooling Technologies will investigate and improve the thermal path from source to sink with the goal of minimizing the temperature rise in your electronics.

( 06/06/2013 / 02:00 PM Eastern Daylight Time / 01:00 PM Central Daylight Time / 11:00 AM Pacific Daylight Time / 18:00 GMT )

On Demand

The DNA Marking Controversy

John Keller, chief editor of Military & Aerospace Electronics, brings his 30-plus years of experience covering the aerospace and defense industry to this interactive webcast.

Mil & Aero Magazine

May 2013
Volume 24, Issue 5
file

Download Our Free Apps



iPhone

iPad

Android

Follow Us On...



M&AE Article Archives

Click here for past articles