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28-nanometer FPGA with PAX Technology Express lane PCI Express Gen3 switch introduced by Altera

SAN JOSE, Calif., 18 Dec. 2011. Altera Corp. (Nasdaq:ALTR) in San Jose, Calif., is introducing a 28-nanometer Stratix V GX field-programmable gate array (FPGA) with Express lane PCI Express Gen3 switch from PAX Technology Inc. (Nasdaq:PLXT) in Sunnyvale, Calif. Stratix V GX FPGAs have hard PCI Express Gen3 IP blocks. Stratix V FPGAs have as many as four hard PCI Express Gen3 x8 IP blocks, which support x1, x2, x4 and x8 lane configurations and provide transfer rates as fast as eight gigabitsps per lane.

Hardening the PCI Express IP blocks in Stratix V FPGAs saves more than 100,000 logic elements compared to soft implementations, Altera officials say. The hard PCI Express Gen3 IP blocks embed the PCI Express protocol stack into the FPGA and include the transceiver modules, physical layer, data link layer, and transaction layer. Stratix V FPGA's PCI Express Gen3 IP targets PCI Express Base Specification Rev. 3.0, 2.x, and 1.x.

The PAX Gene portfolio includes 11 devices ranging from 12 to 48 lanes and three to 18 ports with more configurations in development. For more information contact Altera online at, or PAX Technology at


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