ARLINGTON, Va., 5 Feb. 2012. Computer scientists at the U.S. Defense Advanced Research Projects Agency (DARPA) in Arlington, Va., are asking for industry's help in an effort to develop military embedded systems technology that boosts performance dramatically without increasing size, weight, and waste heat.
The DARPA Microsystems Technology Office on Friday released a broad agency announcement (DARPA-BAA-12-24) for the Power Efficiency Revolution For Embedded Computing Technologies (PERFECT) program, which seeks to increase today's embedded computing efficiency from about 1 billion floating point operations per second per watt (GFLOPS per Watt) to 75 GFLOPS per Watt.
The PERFECT program will do this by taking a revolutionary approach to processing power efficiency, DARPA officials say. This approach includes near-threshold voltage operation and massive heterogeneous processing concurrency, combined with ways to use the resulting concurrency and tolerate the resulting increased rate of soft errors.
The PERFECT program will capitalize on expected industry fabrication geometry advances to seven nanometers, DARPA officials say. Industry contractors chosen to participate in the PERFECT program will not build new hardware, but will develop a simulation capability to measure and demonstrate progress. DARPA is asking for industry research that involves computing hardware and software, concurrency, resilience, locality, and algorithms simulation.
The DARPA PERFECT program seeks to deal directly with some of the primary limitations to advancing military embedded computing: power, thermal management, and size and weight.
Current embedded computing systems have power efficiencies of around 1 GFLOPS per Watt, yet DARPA officials say current needs call for at least 50 GFLOPS per Watt, and at least 75 GFLOPS per Watt will be necessary in the near future.
In the past, embedded computing technology could rely on increasing computing performance with each processor generation per Moore's Law, which anticipated doubling the number of transistors in each new generation, with clock speeds increasing by about 40 percent for each new generation without increasing power density. This allowed for increasing performance without the penalty of increased power.
However, this free ride in processing performance increases is over, DARPA scientists declare, because increasing clock speeds now results in unacceptably large power increases.
The PERFECT program will consist of seven program elements: architecture, concurrency, resilience, locality, algorithms, simulation, and test and verification.
Architecture seeks to develop innovations hardware and software architecture to improve embedded processing system power efficiency. Concurrency seeks to use hardware and software to support high levels of concurrency Resilience focuses on soft errors. Locality looks at minimizing runtime data communication. Algorithms refers to representations of software at a higher level of abstraction than source code. Simulation refers to developing simulation capability to measure and demonstrate progress. Test and verification, meanwhile, will define the benchmark applications to assess research and to assess progress.
Companies interested in participating in the DARPA PERFECT program should send abstracts no later than 23 Feb. 2012, and full proposals no later than 16 April 2012. DARPA officials say they expect to make several contract awards.
To send abstracts and proposals, or for questions or concerns, contact DARPA's Charlie Holland by e-mail at [email protected]. More information is online at https://www.fbo.gov/spg/ODA/DARPA/CMO/DARPA-BAA-12-24/listing.html.
