Officials of Vmetro in Houston are offering a serial front-panel data port (FPDP) IP core for use on Vmetro’s range of Xilinx Virtex-II Pro-based FPGA products. The combination of Vmetro hardware, serial FPDP IP, and user-programmable FPGAs enables high-performance, and integrated solutions for applications that rely on serial FPDP I/O such as signal processing, high-speed data recorders, real-time imaging, and test systems, Vmetro officials say. The FPDP IP core complies with ANSI 17.1-2003 (serial FPDP) and provides creation of point-to-point data links with 1.0625-gigabit-per-second, 2.125-gigabit-per-second, and 2.5-gigabit-per-second FPGA RocketIO connections when using suitable host FPGA cards, company officials say. Using fiber optic transceivers, these data links can range from a few meters to more than 10 kilometers. The IP core occupies a small logic resource footprint in an FPGA; each Serial FPDP interface occupies about 1 percent of a Virtex II Pro version XC2VP70. This enables most of the FPGA to be used for user IP even if several Serial FPDP interfaces are required on one device. For more information contact Vmetro online at www.vmetro.com.