Your recent editorial on the problem of chip heat was spot on, but you missed the most fundamental solution to the problem-don’t create the heat in the first place!

Chip designers face a quandary: as feature size shrinks, speed increases, and the power used for intrachip signals should also shrink. However, traditional interchip (chip-to-chip) signal-transfer solutions require increased power to drive signals through printed circuit boards at higher and higher speeds.

The challenge is that signal power use in the core and I/O must be kept balanced.

In July, SiliconPipe Inc. in San Jose, Calif., publicly demonstrated SuperCharged Copper chip-to-chip interconnect solutions that provide high bandwidth (scalable to 25 gigabits per second) with dramatically reduced I/O power requirements.

A test vehicle using 10-gigabit-per-second serializer/deserializer that required an 800-millivolt peak-to-peak voltage swing to carry signals across a 12-inch trace with one connector, required only a 100-millivolt peak-to-peak signal to transfer signals across a 30-inch SuperCharged Copper trace plus two connectors-more than twice the performance and a power reduction of more than 98 percent.

Today most chips dedicate only 20 to 25 percent of their circuits to I/O and few use 5 GHz clocks, but improved inter-chip interconnects dramatically reduce chip I/O voltage requirements, allowing chip designers to reduce core voltages and dramatically reduce total chip power requirements and resulting heat.

Kevin Grundy