FPGAs enhance military signal-processing applications

Field-programmable gate arrays have become commonplace on signal-processing boards for defense applications such as radar and sonar. The devices promise even more capability down the road, especially in communications technology such as software-defined radio.

By John McHale

The importance of detecting enemy movements anywhere anytime is more critical than any time in history because of today’s global conflicts. This puts more and more demands on signal-processing-intensive applications such as radar and sonar.

Designers of these systems need to meet the performance requirements with power-efficient systems that do not generate excessive heat. Field-programmable gate arrays (FPGAs) solved the power problem by at times doing the work of as many as 12 general-purpose processors (GPPs)-the Freescale Altivec-in one FPGA.

More often in radar than in sonar applications, FPGAs are taking a greater role in signal-processing functionality, says Mark Littlefield, manager of application engineering products at Curtiss-Wright Controls Embedded Computing in Leesburg, Va. They handle fixed-point operations very well and are starting to be able to take on floating-point tasks.

FPGAs provide a well-defined system architecture that enables them to quickly do tasks on the front end of an application that would require multiple Altivec or TigerSharc digital-signal-processor (DSP) chips, says Jeff Milrod, president and chief executive officer of Bittware in Concord, N.H.

However, FPGAs still cannot do floating-point operations such as fast Fourier transforms (FFTs), which need a GPP or DSP, Littlefield adds. They do front-end processing, compressing 12-bit to 14-bit data, then pass it on to the GPP, he says. Curtiss-Wright’s CHAMP family services its DSP business, with the CHAMP 6 debuting soon as one of the first VITA 46 form factors to hit the market, Littlefield says.


MH-60S Seahwaks will be outfitted with the Laser Mine Detection System (ALMDS), which uses VMETRO’s Phoenix CSW1 DSP card is in the Central Electronics Chassis (CEC) system.
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The GPPs and the DSPs still handle the floating-point applications and tasks that may need reconfiguration at some point, but the FPGAs are excellent at digital down-conversion and other front-end filtering, Milrod says.

Bittware’s TigerSharc board is being used for synthetic-aperture sonar applications with preprocessing and cross-correlation in the FPGA and beam forming and ocean modeling performed by the TigerSharc processor. Bittware’s GT3U product is in a missile seeker that also performs video processing, he adds.

DSP systems are more efficient with FPGAs, says Dave Barker, vice president of business development with VMETRO in Houston. “Nearly everyone seems to use Xilinx, but we hear people talking about Altera as well.”

VMETRO has a few different FPGA boards in the VITA 41 form factor with PowerPC 7447As as the signal processor, Barker says.

A lot of VMETRO customers like the fact that high-speed data can be run through the FPGAs with such standards as RapidIO, Barker says. FPGA PMC modules are also popular because of their increased I/O flexibility.

VMETRO’s DSP boards are in Central Electronics Chassis (CEC) system of the Airborne Laser Mine Detection System (ALMDS) program headed by Northrop Grumman. Its boards are embedded in the POD on the MH60 helicopter in a liquid-cooled chassis, Barker says.

The FPGA handles those front-end tasks quickly, spitting out the information for the main processor to handle, says Manuel Uhm, DSP product marketing manager at Xilinx in San Jose, Calif. It makes DSP applications much more efficient.

FPGAs are better suited toward fixed point and can do some floating-point applications and that ability will only improve over time. However, they do perform the front-end analytical “heavy-lifting” functions such as pulse compression that in the past would take multiple processors to do, Uhm says.

These are the types of tasks that need FPGAs and ASICs, Uhm says. DSPs and GPPs are just not as efficient when it comes to size, weight, and power, as are FPGAs, Uhm adds.

IP Cores

PowerPC Cores are available for FPGAs, but many in the industry do not believe they are ready for full-blown floating-point operations.

“We have a PowerPC Core 405 on V4 and 440” on the Virtex 5 but they are not powerful enough to do all the functions a GPP or DSP do, Uhm says. Processor cores are not bringing anything to the table just yet, Barker agrees.

Signal processing challenges for FPGAs

The biggest challenge is power, Uhm says, especially for military applications such as man-portable radios, in which a small footprint, low weight, and low power are the requirements.

FPGAs solved a power issue for processors by doing the work of multiple processors on one FPGA, and now designers are working at improving the power efficiency of the FPGAs themselves, Uhm explains.

The Xilinx Virtex 4 has a 50 percent improvement in dynamic power efficiency and a 30 percent improvement in static power efficiency over the previous version, Uhm says. The Virtex 5 will be even more power efficient, he adds.

Uhm declined to comment on the method behind the power improvements, citing proprietary designs as the reason.


The Virtex-4 SX field-programmable gate array from Xilinx is FPGA optimized for DSP applications.
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Another issue with FPGAs is the difficulty in reconfiguring them, Milrod says. They usually are not partially reconfigurable and the entire FPGA has to be re-architected, he says. The man-hours necessary are not worth the effort, Milrod notes.

With GPPs and DSPs it is easier to do because it is done through software embedded in the silicon, Milrod explains. The difficulty of programming in VHDL also does not help, he adds.

Uhm says that is changing as Xilinx will be offering partial reconfigurability in future FPGAs.

FPGAs for software defined radio

One place in which FPGAs will play a major role is communications, specifically software-defined radio (SDR), Milrod says. This technology is growing commercially and will also grow within the military, he adds.

The big picture is that FPGAs fit right into the SCA (Software Communications Architecture) framework on which SDR is based for the Joint Tactical Radio System (JTRS), he says.


The ChampFX single-board computer for DSP applications from Curtiss-Wright Controls Embedded Computing uses FPGA technology.
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FPGAs are crucial for these applications, and offer size, weight, and power advantages, Uhm says. For example the JTRS MHO program, which is the man-portable element of the JTRS program has very low power requirements because it must match the wattage of the old radios, which had a limit of 5 watts, Uhm explains.

TigerSharc

The demise of the Analog Devices (ADI) TigerSharc DSP is exaggerated, but there are not many shops that still produce designs based on it as well as Bittware.

One of the reasons was that ADI did not manage its third parties or backward compatibility well, Milrod says. Now the Altivec offers much more third-party support and therefore has gained market share over ADI’s products.


The GT3U TigerSharc DSP board from Bittware is in missile applications.
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However, Milrod says, the TigerSharc is still the superior chip. If performance is the main consideration then The TigerSharc is the best choice, he adds. Milrod and his team at Bittware are working on developing software tools and other techniques to make third-party support not as necessary for the TigerSharc as it is today.

Software key for future DSP applications

Developing a software tool that removes the burden of supporting the processor system from the customer is key, Milrod says, and is why so many hardware companies are hiring software engineers.

Radstone experts believe they are on the right track in this area with their AXIS-Advanced Multiprocessor Integrated Software. The solution is a performance-optimized software environment designed to accelerate the development and production deployment of complex signal-processing applications requiring multiprocessor PowerPC Systems. The integrated modular architecture provides significant flexibility, enabling the engineer to select the functionality required for the specific task with the ability to reconfigure or scale the system to meet future application demands, Thomson says.

Speaking of FPGAs, AXIS is designed to make efficient use of them as well, since they handle most of the front-end processing in Radstone’s PowerPC-based boards, Thomson says.

The core of the software architecture consists of three integrated software elements, Interprocessor Communications, Multiprocessor Productivity Tools, and Optimized High Performance Digital Signal Processing Libraries.

AXIS sits on top of the real-time operating system with parts of it acting as a middleware, Thomson says.

AXISFlow handles the interprocessor communications. It provides high throughput, low latency, and reconfigurable interconnects that facilitate data transport between tasks, processors, boards, and systems that can seamlessly scale.

AXISView, which comprises the multiprocessor productivity tools, simplifies the complexity of the underlying hardware with visualization and graphics tools, ensuring ease of use while maximizing user efficiency, combined with system monitoring and tracking functionality for optimal system performance.

AXISLib, the optimized high-performance digital signal-processing libraries, adheres to industry standards with comprehensive support for Signal and Vector Processing functionality with the most important algorithms tuned for the PowerPC AltiVec architecture.

According to Thomson, the software is designed to work with Radstone systems and is not sold separately.


Synplicity and Actel strengthen relationship for EDA solutions

Synplicity in Sunnyvale, Calif., and Actel Corp. in Mountain View, Calif., announced that the companies have expanded their OEM agreement to provide an on-going technology roadmap for Actel customers. Under the terms of the multiyear agreement, Actel obtains the right to distribute the Synplify Pro, Identify and Synplify DSP software solutions to its customers as part of its Libero Integrated Design Environment (IDE). The expanded agreement will also provide Actel customers with future access to Synplicity’s innovative physical synthesis technology.

“Actel delivers a broad range of advanced FPGA solutions, including its low-cost ProASIC3 for value-based applications, high-density RTAX-S for space applications and the new Actel Fusion Programmable System Chip family, which is unique in its ability to support mixed-signal designs,” says Joe Gianelli, Synplicity’s vice president of business development. “We have been working closely with Actel to optimize our leading-edge technologies to capitalize on the features of these architectures. We believe that through this close partnership, we can offer Actel’s customers advanced design tools that will enable them to achieve optimal device performance.”

This expanded OEM agreement leverages the strengths of each company to improve the FPGA designer’s experience.

This agreement also bolsters Actel’s hardware debugging capabilities by adding the Identify RTL debugger to the Gold and Platinum versions of the Libero IDE. The Identify product is a debug-centric verification tool that offers the fastest method of finding errors in a design by providing simulator-like visibility into a live, running FPGA. The Identify RTL Debugger is the first tool to allow designers to instrument and debug directly in RTL source code, Actel officials say.

For designers of DSP systems, the addition of Synplicity’s Synplify DSP software to the Libero IDE enables a seamless flow from The Mathworks’ Simulink design environment to RTL design. Synplify DSP software uniquely uses proprietary system-level synthesis algorithms to automatically generate highly optimized RTL code ready for logic synthesis, eliminating prior hand-coded, error-prone and time-consuming methodologies requiring numerous iterations between the DSP algorithm architect and the RTL hardware designer.

Actel’s Libero IDE offers best-in-class tools from leading third-party EDA vendors and custom-developed tools from Actel integrated into a single FPGA development package. The Libero tool suite supports mixed-mode design entry input, giving designers the choice of mixing either high-level VHDL or Verilog HDL language blocks with schematic modules in a design.

For more information about Actel, visit www.actel.com. For more information on Synplicity visit www.synplicity.com.


BAE Systems selects VMETRO conduction-cooled processors

VMETRO received a contract to supply conduction-cooled Phoenix VPF1 digital-signal-processing boards to BAE Systems in Nashua, N.H., for the U.S. Army’s Tactical Signals Intelligence Payload (TSP) Program. The Phoenix VPF1 Dual PowerPC, Dual Virtex-II Pro FPGA VME/VXS digital signal processors will run the signal-processing algorithm as well as perform real-time processing of the sensor data. The initial contract is valued at approximately $500,000. The design is being included in similar programs as part of BAE Systems’ common-platform initiative.

TSP is a subsystem intended for the Army’s tactical Unmanned Aerial Vehicles (UAV). The payload collects and processes radio-frequency energy, which will be displayed on the payload operator’s workstation in a ground processing facility. The system provides the ground tactical commander with an airborne collection capability that is responsive to real-time emerging operational intelligence requirements. TSP will provide a critical capability to see and understand the enemy on future battlefields.


The Phoenix VPF1 DSP board from VMETRO is part of the U.S. Army’s Tactical Signals Intelligence Payload program.
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“VMETRO was chosen for BAE Systems’ TSP program because its innovative technology provides the performance and scalability needed as well as the deployable capabilities required during the life of this program,” says Eric Vogel, BAE Systems’ program manager for TSP. “Furthermore, VMETRO’s technical support and value-added applications engineering will enable BAE Systems to deploy these products quickly.”

For more information visit www.vmetro.com.


Mercury Computer Systems announces conduction-cooled COTS computer system

Mercury Computer Systems, in Chelmsford, Mass., announced the breakthrough PowerStream 6600 multicomputer, with 716 PowerPC GFLOPS of compute performance in a conduction-cooled enclosure, to enable powerful sensor computing on the move.

The performance density and rugged mechanical design of the PowerStream 6600 enables manned and unmanned vehicles to support C4ISR (command, control, communication, computers, information, surveillance and reconnaissance) multimode missions. These include radar, and image and signals intelligence (SIGINT) processing, Mercury officials say.

“The PowerStream 6600 contains the enabling hardware and software building blocks necessary for mission systems to perform compute-intensive tasks, such as processing a 3-D radar data cube, in real time,” says Eran Strod, director of product marketing for the Defense business at Mercury.

The PowerStream 6600 has the processing capacity to enable advanced radar applications including multimode search, multitarget tracking, synthetic-aperture-radar (SAR) imaging, and space-time adaptive processing (STAP). Additionally, multimode sensor signal processing can be supported for cross-cueing of SIGINT detections with SAR or other imagery sensors aboard a mobile platform.


Mercury Computer Systems’ PowerStream 6600 system is an integrated, conduction-cooled multicomputer based on the VPX-REDI (VITA 46 and 48) draft standards for next-generation data acquisition, processing, and I/O in a wide range of environmental conditions.
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The 16-slot PowerStream 6600 is a system computing solution with data acquisition, high-speed I/O, PowerPC compute clusters, and FPGA processing integrated with open-standard software. From the inside out, the PowerStream 6600 is built using open and de facto standards: the Linux and VxWorks operating systems, Internet Protocol (IP), VPX-REDI (VITA 46 and 48), PMC-X/XMC, Ethernet, and the RapidIO interconnect fabric. The PowerStream 6600 is aligned with open standards initiatives such as the Navy’s Open Architecture Computing Environment (OACE).

The PowerStream 6600 supports 34 gigabits per second of sustained RapidIO fabric throughput without requiring slots dedicated to fabric switching. Maximally configured, it can support either 64 processors or 21 FPGAs. The following modules will be available with first customer shipment:

  • quad 1.4 GHz MPC7448 high-compute-density (HCD) card;
  • FPGA compute node (FCN) board featuring three user-programmable Virtex-4 Processors; and
  • dual MPC8548 smart carrier board supporting dual PMC-X or XMC mezzanine I/O cards.

The PowerStream 6600 provides a path forward for Mercury’s MCOE software environment, as well as enhancements. The platform software supports the IP, enabling processors to be deployed as a network cluster running standard networking applications. This network-enabled software architecture will ease the challenge facing developers who must support multimission computing and connect next-generation sensors to the global information grid (GIG), company officials say. Applications will also benefit from having a wide range of data movement middleware options, including TCP/IP, CORBA, MPI, DRI and PAS, all optimized to run over the RapidIO backplane fabric.

PowerStream 6600 is scheduled to ship to customers the end of this year. For more information on the PowerStream 6600, visit www.mc.com/conductioncooled, or contact Mercury at (866) 627-6951.


Curtiss-Wright introduces PowerMatrix multiprocessor computers

Officials at Curtiss-Wright Controls Embedded Computing in Leesburg, Va., announced the new PowerMatrix family of multiprocessor systems.

These fully configured, high-performance/high-density systems offer a wide range of configuration flexibility with versions supporting from 10 to 48 processors. The PowerMatrix-48 DSP, a 21-slot rack-mount system supports as many as 48 PowerPC 1.25 GHz processors and delivers up to 480 GFLOPS peak performance. The PowerMatrix-10 SMP, an 8-slot rack-mount system supports as many as 20 PowerPC 1.0 GHz processors for peak performance of as much as 160 GFLOPS.

PowerMatrix systems have spare VME slots and PMC sites to build custom configurations ideal for applications such as radar, sonar, and signal intelligence that require massive processing coupled with broad I/O support.

The systems will be offered with independent node architecture boards running VxWorks real-time software and symmetrical processing (SMP) architecture boards running Linux.

“Our customers are increasingly looking for integrated multiprocessor system solutions,” says Lynn Patterson, vice president and general manager of Curtiss Wright’s Modular Solutions group. “Our PowerMatrix systems are ready to go out of the box, freeing our customers to focus on software development rather than systems integration.”

The PowerMatrix systems are modular and may be easily customized to meet specific processing and I/O requirements. Examples of I/O options offered on the PowerMatrix systems include Serial FPDP, Fibre Channel, Gigabit Ethernet, ARINC 429, and digital receivers.

The PowerMatrix-48 DSP can support as many as 12 quad Champ AV4 PowerPC cards and two 12-port StarBlade StarFabric switches. Each of the Champ AV4 cards is connected to the full mesh StarFabric via a StarLink II PMC card.

This system is ideal for demanding signal intelligence and airborne SAR radar applications, Curtiss-Wright officials say.

The PowerMatrix-20 SMP supports five quad PowerPC Manta QX3 single-board computers, one PSTN StarFabric PMC, and one PGR8 Gigabit Ethernet Switch PMC. The Gigabit Ethernet Switch card is also provided to connect all of the Manta QX3 cards to the Gigabit Ethernet backplane. This compact system is ideal for the medium-level processing typically required by ground-mobile and fast-jet radar applications.

For more information, visit www.cwcembedded.com.


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