By John McHale
ANDOVER, Mass.—Instead of waiting for the commercial industry to come up with high-performance integrated circuits (ICs), experts at Raytheon Integrated Defense Systems (IDS) and the Defense Advanced Research Projects Agency (DARPA) are demonstrating that affordable, high-performance circuits for military applications can be produced by growing semiconductor compounds directly on silicon.
“We’re pushing the state of the art ahead, instead of waiting for the commercial world to get around to it,” says Tom Kazior, program manager at Raytheon IDS in Andover, Mass. They could do it but have a slower time horizon and are more concerned with the return on investment, he adds.
The work is part of a $6.5 million contract funded by DARPA in Arlington, Va., and awarded through the Office of Naval Research. It is a building block within DARPA’s Compound Semiconductor Materials on Silicon, or COSMOS, program.
“Our team’s process of directly growing a semiconductor compound on a uniquely engineered silicon substrate provides a technical approach that is creating a class of integrated circuits that will be more affordable for our Defense Department customers,” says Mark Russell, vice president of engineering at Raytheon IDS.
“Selective placement of semiconductor compounds on silicon is an important achievement because it proves that optimal circuit performance can be produced through a heterogeneous, high-yield, monolithic integration process,” Kazior says.
“We want to start with basic silicon integrated circuits, getting millions and millions of transistors on a chip,” enhancing the performance of the integrated circuit by selectively adding compound semiconductor where it is necessary, he continues.
Raytheon’s approach is to partner with a commercial foundry to build the circuits, Kazior says. Starting up a silicon foundry is prohibitively expensive, costing as much as $1 billion and Raytheon is not interested in building a billion-dollar foundry, nor is any defense contractor, he explains.
Since operational and start-up costs are so high, foundries are averse to introducing materials into their system, Kazior says. Raytheon and its team are developing their formula as research and development to demonstrate to prospective foundries that it will not mess up their CMOS process, Kazior explains.
Raytheon is looking to replace the silicon-germanium HBT with indium phosphide HBT, he says. If you get rid of germanium HBT and introduce indium phosphide HBT in its place it “runs an order of magnitude faster, resulting in faster circuits,” Kazior notes.
The concept is analogous to when the silicon-germanium HBT material was added to CMOS, Kazior says. The existing CMOS process remained intact while the Silicon germanium HBT was added, he explains. “We are using the existing CMOS and integration process, just replacing the germanium HBT with indium phosphide,” Kazior says.
The challenge is that indium phosphide is what is called a dopant compound on the Periodic chart and can change the conduction scope of a chip, Kazior continues. “We have to engineer indium phosphide to work with existing silicon so it doesn’t interfere with the foundry’s process, thereby retiring the risk,” he says.
Raytheon’s team already includes two foundries—Raytheon Systems Limited in Glenrothes, Scotland, and Silicon Valley Technology Center in San Jose, Calif. “We’re in Phase 1 of the DARPA COSMOS program”—creating the first wafers at Scotland facility, Kazior says. That should be completed by the end of the year.
The Scotland facility is a 4-inch diameter foundry that will help demonstrate the concept, he says. Once it is proved at the Scotland foundry, the next step is to take it to Silicon Valley Technology Center (SVTC), an 8-inch diameter foundry that is much more modern, Kazior continues. “SVTC is a spin-off of Cypress Semiconductor and is an R & D foundry for hire,” he notes. Once it is demonstrated at SVTC, the Raytheon team will take it to a “big time silicon foundry” for production, Kazior says.
There will be some retooling costs when replacing the germanium HBT with the indium phosphide, Kazior says. However, the goal is to make this process as smooth as possible for the foundry, he adds.
“We don’t want to reinvent how to make CMOS, but make sure as we add indium phosphide we don’t disrupt the CMOS fabrication process,” Kazior says.
Other Raytheon IDS teammates on the COSMOS project are: Teledyne Scientific Imaging Co. in Thousand Oaks, Calif.; Massachusetts Institute of Technology in Cambridge, Mass.; Paradigm Research LLC in Windham, N.H.; IQE in Bethlehem, Pa.; and Soitec in Grenoble, France.
