BY Justin Moll

The VPX architecture has been successful since its inception in 2007. With its high-speed performance using the MultiGig connector, wealth of available I/O, rugged form factor, and design flexibility, it has taken the military and aerospace industry by storm. In late 2008 and early 2009, grumblings about the architecture's wide-open flexibility creating interoperability issues turned into a loud chorus. Therefore, the OpenVPX initiative commenced in early 2009, with a goal to provide interoperability definitions for the VPX specification.

The initiative was rolled into the VMEbus International Trade Association (VITA) as the VITA 65 specification, which is expected to go through ANSI approval in June 2010. It would take too much text and likely to be too confusing to go through every aspect of OpenVPX, so we will focus on the technology from the backplane perspective.

OpenVPX simply provides definitions for backplane configurations and the module and slot profiles that are used therein. The module and slot profiles ensure that a vendor's VPX boards have pinouts that are interoperable within the VPX backplane slots. The backplane configuration tells the user which slot profiles are used, including the data rate, routing topology, and fabric used.

Functionally on the backplane, the whole 425-page specification only changes two pins. OpenVPX redefined two reserved P0/J0 signals Aux_Clk (+/-) and added one P1/J1 single-ended utility signal of Maskable Reset and redefined the Res_Bus signal to GDiscrete. The Aux_Clk and GDiscrete pins were already bused anyway, so there is minimal effect. The SysCon signal is also now configurable; however, the OpenVPX effort isn't really about functional changes, it's about definitions.

Defining backplane configurations

For the backplane, the backplane topology chart is a good starting point on the overall composition of its design. It shows the topology across the expansion plane, data plane, control plane, and system management (IPMB) and utility buses. From here, we can learn quite a bit about the layout of the backplane. The topology across the data plane will let us know the core fabric topology, like whether it's a star, ring, or mesh design. Next, we need to look at the backplane profile to understand what types of specific slots it contains.

The backplane profiles tell us what slot profiles are incorporated, the pitch, and the data rate. The profile name gives us some basic information about the backplane. So, in the 3U backplane example, this is its profile name: BKP3-DIS06-15.2.14-1

BKP = backplane
3=3U
DIS = Distributed mesh topology
06=6 slots
15.2.6 = VITA 65 specification section location of this configuration
-1 =

The profile segments, such as height, slots, and location, in the specification are easy to figure out. The "DIS" in the part number may be more confusing. The main fabric topologies are CEN for Centralized, DIS for Distributed, and HYB for Hybrid. "Centralized" means it has a centralized switch slot and the routing could be similar to a Star topology. "Distributed" has the interconnections across the slots like a mesh or a ring. "Hybrid" in this case refers to a hybrid of serial VPX slots and parallel slots like VME64x (CompactPCI is another possibility, too). In our 3U backplane example, the backplane topology chart showed a "five-slot ring", which is a twisted ring routing design. In the backplane profile number, we know that this is defined as a Distributed architecture.

The backplane profile summary in the specification also describes the slot types (payload, switch) and the communications plane topologies which describes the number/type of signal (fat pipes, thin pipes, ultra thin) across the control, data, and expansion planes. The slot type is also further defined. The DIS and CEN configurations typically have Payload and switch slot types. The HYB will typically also define Peripheral, bridge, and bus slot types like VME to account for connections to the legacy bus slots. The Bridge slot does not mean an active bridge board (like a CompactPCI Bridge) is being used; it refers to the fact that this VPX slot has pinouts defined for the parallel bus (like VME).

Defining modules and slot profiles

VPX Modules will utilize different type of signal links, such as Fat Pipes with 4 links (4 Tx pairs + 4 Rx pairs), Thin Pipes with 2 links, and Ultra Thin pipes with one link. The wider bands like Fat Pipes are typically used in the data plane, while the control plane will often have the thin pipe or ultra thin-pipe signals. OpenVPX provides definitions for the payload and switch slot modules.

So, when we look at the backplane topology, backplane profile, and the corresponding slot profiles, we can understand how a VITA 65 backplane is configured. With this information, we can see which cards, with specific slot profiles, are compatible with each backplane.

It's not only important for your backplane provider to understand the OpenVPX configurations, it's critical they understand the VPX ecosystem. Issues such as cooling and board specifications and configurations are critical to VPX success.

Make sure your provider is familiar with the associated industry products lines, design considerations, and potential pitfalls of the full VPX ecosystem. It's important to remember that not all VPX backplanes need to be or will be compliant to VITA 65 (OpenVPX).

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JUSTIN MOLL is director of marketing at Elma Bustronic Corp. in Fremont, Calif. He can be reached by e-mail at Justin.moll@elmabustronic.com. Contact Elma Bustronic online at www.bustronic.com.

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