Leveraging the DSP capabilities of FPGAs in electronic warfare systems

BY IAN LAND, ALTERA CORP.

SAN JOSE, Calif.–Electronic warfare (EW) systems traditionally used standalone digital signal processors (DSPs). Today, field-programmable gate arrays (FPGAs) incorporate multiply and accumulate elements (MACCs) that perform digital signal processing calculations in parallel with higher performance than DSPs.

MACC elements have a multiplier and an adder which performs the accumulate function, helpful for performing filtering and Fast Fourier Transforms (FFTs). Some elements incorporate further optimizations, such as pre-adders, to combine data prior to the multiplier, reducing multiplier counts for symmetric filters and incorporating the filter coefficients within the DSP processing element. Advanced DSP elements offer variable precision, excellent for applications such as receiver-jammers, which require filtering, and decoys, which need space-efficient DSP processing. DSP blocks in FPGAs are designed to support integer calculations, meaning whole numbers from 0 to the maximum size supported by the multiplier bit width. More advanced elements can efficiently support floating-point processing, which is similar to scientific notation where the binary point (equivalent to the decimal place in base10) can "float" in the mantissa while the exponent can be used to represent a much higher dynamic range without overflow or truncation errors.

True floating point, where each number can independently vary its exponent, improves the numerical precision to enable system performance, such as real-time and low-latency interference processing as well as distant early warning target detection. Recent innovations in FPGA DSP processing elements and tool flow allow for high-performance floating point to be implemented in numerically sensitive portions of EW processing systems.

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February 2014
Volume 25, Issue 2
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