Anemone FPGA-based co-processor introduced by BittWare to simplify digital signal processing for radar and SIGINT


CONCORD, N.H.—BittWare Inc. in Concord, N.H., is introducing a numeric co-processor for field programmable gate array (FPGA)-based embedded computing systems that require complex or changing processing algorithms, such as radar processing, signals intelligence (SIGINT), and software-defined radio (SDR). The BittWare FPGA co-processor, called Anemone, is a floating-point processing engine that is programmable in the C computer language.

The Anemone chip, designed to function with FPGAs from Altera Corp. in San Jose, Calif., has processors that together provide 32 billion floating-point operations per second while consuming two watts of power. The FPGA co-processor is based on the Epiphany architecture from Adapteva Inc. in Lexington, Mass.

The Anemone FPGA co-processor can make designing digital signal processing (DSP) systems with Altera FPGAs well rounded and versatile, explains Jeff Milrod, BittWare’s president and chief executive officer. Anemone “bolts on seamlessly to your FPGAs and adds a huge safety valve,” Milrod says. “FPGAs and their development tools are still limited, are still a very complex development environment, and are not friendly to algorithms that change quickly.”

Systems designers can connect several Anemone chips to scale up to compute blocks as large as 4,096 processors that provide compute performance of eight trillion floating-point operations per second. “The attraction is for people who are good at FPGAs and have some FPGA resources, but not enough,” Milrod explains. “They can have the FPGA do what it’s good at, and have the processor do what it’s good at.”

Using the Anemone chip can make designing with FPGAs easier than it is today because the Anemone runs in the C programming language. Using FPGAs alone can be difficult because these devices require skill with the VHSIC Hardware Description Language (VHDL), which not all companies have.

Making FPGAs easier to use will make an Anemone/FPGA architecture competitive with embedded computing that relies on general-purpose processors (GPPs) like the 2nd Generation Intel Core i7, as well as on graphics processing units (GPUs) like the Nvidia CUDA. The beauty of an Anemone/FPGA architecture is: it is physically smaller and lighter, and it consumes less power than a GPP/GPU architecture, Milrod says.

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BittWare is raising the stakes in the digital signal processing game with its introduction of an FPGA-based co-processor called Anemone, which could simplify the use of field-programmable gate arrays in DSP systems.

BittWare will release products this summer based on the Anemone FPGA co-processor and Altera FPGAs packaged on commercial off-the-shelf (COTS) boards in form factors such as the VITA-57 FPGA Mezzanine Card, Advanced Mezzanine Card, 3U VPX, and PCI Express.

BittWare designed Anemone for complex signal processing, and the chip is more efficient for this job than are traditional floating-point digital signal processing chips, Milrod says. Each Anemone chip has 16 eCore processors, each with a general-purpose instruction set, which perform floating-point computations as single-precision IEEE 754.

“Our machine,” Milrod explains, “can do one instruction at a time and one load store at a time. There is no caching, so you have direct control over the memory structures. There is no funny business with extensions, SIMD, or subsets; it’s straight-up ANSI C. Anything you have in ANSI C will run right out of the box on our machine. It won’t be optimized, but it will run.”

BittWare has an exclusive license to use the Adapteva Epiphany architecture in aerospace and defense applications. The Anemone chip is based on the 16-core, four-link-port version of the Epiphany silicon demonstration platform, which includes the processor and memory interconnection mesh. Adapteva remains free to market intellectual property for ASICs and SOCs, and for licensing the architecture and processor technology to other companies.

Although the Anemone/FPGA architecture aims at many of the same floating-point-intensive embedded computing applications in which the GPP/GPU architecture is becoming popular, Milrod says it might not make sense to convert systems that are already using the GPP/GPU approach.

“For someone not using FPGAs, but who is doing everything in Nvidia graphics without major power problems, then this probably won’t be very attractive to him,” Milrod says. “If they are already down that road, this does not add any value, but if someone is starting from scratch, this is a new signal processing alternative.”

Some applications where the Anemone/FPGA architecture would make the most sense include handheld and soldier-worn computing systems, unmanned vehicles, and other applications where size, weight, and power consumption are driving concerns.

Milrod also envisions the Anemone/FPGA architecture’s use in advanced phased-array radar systems in which a separate processor could be placed at each radar element to speed signal filtering and conversion from analog to digital signals. “This is low-enough power to do that,” Milrod says.


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February 2015
Volume 26, Issue 2

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