KIRTLAND AIR FORCE BASE, N.M.-U.S. Air Force and NASA experts are kicking off a program to define a next-generation, radiation-hardened microprocessor for space applications based on anticipated space computer needs from 2020 to 2030. The Air Force and NASA want to define a space-qualifiable rad-hard multicore processor architecture for manned and unmanned spacecraft.
The Air Force Research Laboratory (AFRL) released a presolicitation (BAA-RVKV-2013-02) for the Next Generation Space Processor (NGSP) Analysis program, which seeks to perform a three-month evaluation of anticipated space computer applications for 2020 to 2030, and then distill a set of goals for a future space microprocessor architecture.
Sponsoring the NGSP Analysis are the AFRL Space Vehicles Directorate (AFRL/RV) and NASA Space Technology Mission Directorate-Game Changing Development (NASA/STMD-GCD) program. The NGSP Analysis program will produce a simulation model of the proposed processor architecture that will predict the processor's power use.
|The U.S. Air Force and NASA are defining a next-generation, radiation-hardened microprocessor for future manned and unmanned spacecraft.|
Benchmark applications will include autonomous pinpoint landing with hazard detection and avoidance during entry, descent, and landing of missions to the moon and Mars; real-time segmented mirror control for large space-based telescopes; onboard real-time analysis of multi-megapixel-level hyperspectral image data; autonomous onboard situational analysis and real-time mission planning; and real-time, model-based, spacecraft-level fault protection.
A follow-on program, potentially worth as much as $20 million, would develop a space microprocessor for high-performance space computing for advanced space missions through 2030. The microprocessor will be based on commercially available microprocessor technology modified for space applications, Air Force researchers say. High-speed Experts say they want the Next Generation Space Processor to execute several concurrent applications and parallel processing across the set of cores; have at least 24 processor cores that support 32-bit words, have at least one terabyte of memory, and support floating-point processing.
The next-generation space processor must perform 24 billion operations per second and 10 billion floating-point operations per second and consume no more than seven watts of power, with the ability to turn off unused cores and other resources. The processor must have a sleep mode in which it consumes no more than 100 milliwatts of power, and prevent errors by enforcing partitioning of groups of cores, interconnects, and memories into fault-containment regions.
The processor also must support DMA transfers between external I/O ports and external memory, and have a non-volatile memory boot ROM port able to boot the processor, four to eight DDR3/4 memory ports, eight 10-gigabit-per-second serial I/O ports, industry-standard interfaces, a generic serial interface that connects to an external protocol converter, such as a field-programmable gate array or custom device, and a serial interface to an FPGA or other reconfigurable co-processor.
The NGSP must have a dedicated test and debug interface; operate cascaded or tiled devices; have symmetric and asymmetric hypervisor software; run the Linux operating system; and have a C and C++ application software compiler.
FOR MORE INFORMATION visit www.fbo.gov/spg/USAF/AFMC/AFRLPLSVD/BAA-RVKV-2013-02/listing.htm.