The 52663 uses an optimized IP core for the Xilinx Virtex-6 field-programmable gate array (FPGA) for mobile monitoring systems that must capture some or all of the 1100 uplink and downlink signals in upper and lower GSM bands.
The model 52663 accepts four analog inputs from an external analog RF tuner where the GSM RF bands are down converted to an IF frequency. Four A/D converters then digitize these IF signals and route them to four channelizer banks, which perform digital downconversion.
Two of the banks handle 175 channels for the lower GSM transmit/receive bands and two banks handle 375 channels for the upper bands. The DDC channels within each bank are equally spaced at 200 kHz.
Each DDC output is re-sampled to a 4x symbol rate of 1.08333 MHz to simplify symbol recovery. Every four DC outputs are combined into a frequency-division "superchannel" that allows transmission of all 1100 channels across the PCI Express Gen 2 x8 interface.
The GSM channelizer IP core is supported with additional factory-installed FPGA functions including packet formation, time stamping, four DMA controllers, gating and triggering. Baseband super-channel packets are sent via DMA controllers to processor memory where customers apply processing algorithms.
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Ground or airborne monitoring platforms can scan the entire GSM spectrum for all uplink and downlink signals. Pentek's ReadyFlow Board Support Package for Linux and Windows operating systems have drivers and high-level C-callable library functions
For more information contact Pentek online at www.pentek.com.
