By Rodger H. Hosking
Designers of open-architecture embedded systems who face constant market pressures must always consider ways to take advantage of the latest processors and peripherals. The silicon vendors are doing their part by steadily pushing up clock speeds and data transfer rates. Yet the standard board, bus, and backplane technologies available today often are the chief culprits in limiting overall system performance.
As an example, the recently-introduced Texas Instruments TMS320C6203 digital signal processor (DSP) executes eight 32-bit instructions in parallel at a 300 MHz rate, yielding 2.4 billion instructions per second of peak operation. The chip joins an on-chip multiple-path arithmetic logic unit and four-channel direct memory access (DMA) controller to support extremely high-speed I/O peripherals. Using 32-bit parallel data buses, it can move data to I/O devices at a combined rate of 1,800 megabytes per second.
With board vendors packing four to eight of these devices on a board, keeping each processor supplied with sufficient I/O bandwidth becomes ever more difficult. Attempting to meet the data transfer rates of fast communication links such as RACEway, FPDP, Fibre Channel, and high-speed peripherals like wideband A-D converters stresses traditional I/O structures to the breaking point, and drives home the need for a better solution.
One well-proven method of delivering dedicated, high-speed processor interconnects is the mezzanine, or daughter board. Unfortunately, the bandwidths of most popular standard mezzanine buses still fall far short of meeting the needs of recently introduced DSPs and reduced instruction set computer (RISC) architectures.
Mezzanine design objectives
To address this I/O throughput gap for their new Model 4290 Quad `C6201 DSP Board, engineer from Pentek Inc. of Upper Saddle River, N.J., evaluated all existing mezzanine standards. Although they considered PMCs (PCI Mezzanine Cards) as candidates, they soon discarded them because the maximum PCIbus transfer rate of 33 MHz was too low for many high-speed peripherals. In addition, a standard 6U VME board can accommodate only two PMC sites, which forces two DSPs to share one PMC site.
Instead, Pentek designers realized they needed a mezzanine structure fast enough to provide a private parallel data path to each processor supporting at least 100 MHz transfer rates for 32-bit words. This is consistent with the synchronous bus cycle mode of the `C6201 and a realistic upper limit for connector technology. In addition to a parallel path, the mezzanine had to support serial interfaces for compatibility with numerous data-acquisition and telecommunications peripherals.
Lastly, the mezzanine needed to control and provide status functions easily for the circuitry on the mezzanine module. Mechanically, the electrical interconnection scheme had to be small, robust, reliable and reasonable in cost. Front-panel access for signal interfaces and connectors was essential.
Since no existing mezzanine standard could meet these requirements, Pentek embarked on a new mezzanine design. The mezzanine architecture had to be non-proprietary to help ensure acceptance from a broad industry base, royalty-free, and completely independent of any one processor or manufacturer.
VIM: Velocity Interface Mezzanine
The resulting mezzanine specification, dubbed VIM for Velocity Interface Mezzanine, defines a high-performance mezzanine bus that transfers data quickly, and supports several board formats. The open-standard VIM not only provides an I/O solution for current generation TI processors, but also supports new DSP and RISC devices from other manufacturers, consistent with the open standard mandate.
The essential elements of the VIM electrical bus consist of three interfaces: the streaming parallel bus, the serial interface, and the control/status interface.
No open architecture bus should rely on the specific timing characteristics of any single processor or manufacturer. Pentek engineers elegantly decoupled VIM`s high-speed 32-bit streaming parallel interface from the processor bus by using synchronous, bi-directional FIFO memories, or synch Bi-FIFOs.
Synch Bi-FIFOs provide consistent, industry-standard timing and have the added benefit of buffering input and output data to the processor to take advantage of efficient block transfers. The DMA controllers that support the processor can use the software-configurable interrupt flags of the Bi-FIFOs for automatic data transfers between the processor memory and peripheral devices, thus freeing the processor core to concentrate on important tasks.
With independent input and output ports, the Bi-FIFO supports wide disparities between mezzanine data rates and processor data rates. The mezzanine port can clock as fast as 100 MHz to support fast and slow peripherals as well as periodic or non-periodic clocking, depending on the nature of the device. This frees the processor from preparing itself to take or deliver data at just the right time, which can impose a serious constraint on processing tasks.
On the processor side, the Bi-FIFO can load or unload when convenient, usually at the end of a processing loop when block transfers of data make the most sense. Prudent real-time signal processing design techniques require the processor task execution time for a block of data to be shorter than the time it takes to collect that block. With this approach, the processor completes the processing loop before the next block is ready. Bi-FIFO buffering embodies the ideal implementation of this approach.
Systems designers can configure VIM Bi-FIFO status flags for empty, full, and other programmable levels as interrupt inputs to the baseboard processor. This enables full use of the DMA controllers found in most processors.
The VIM serial interface supports two synchronous full-duplex channels, each with two data lines, three clock lines, and two framing signals. Many of the new processors feature integral serial ports, often with sophisticated framing and TDM hardware conveniently linked to DMA controller signals. This nicely supports serial streams from digital telecommunications interfaces like E1/T1 and matches the processing functions of the telecom-oriented DSPs.
The VIM random access control/status bus, which closely resembles a generic microprocessor interface, controls the interfaces and circuitry on the mezzanine module. This allows the device to map registers and other programmable resources on the module into a read/write address region of the processor memory space.
Power supply lines from the motherboard include several pins for +5 volts DC and ±12 volts DC. Pentek designers recommend power dissipation of no more than 15 watts.
Pentek designers chose pin and socket style connectors for the baseboard/module interconnect because of the connectors` reliability. These small 160-pin, four-row connectors have male and female types in surface-mount versions to conserve board real estate.
Quad DSP VIM Baseboard
Pentek experts first implemented VIM on the Model 4290 Quad `C6201 DSP processor on a standard 6U VMEbus board. Each of the four processors features its own private VIM interface, allowing simultaneous full-bandwidth transfers in and out of each processor. They arranged four VIM connectors in one line parallel to the front panel.
Pentek designers defined several different mezzanine module form factors within the VIM specification. The first and most popular is the VIM-2 format, which has a front panel that becomes part of the front panel of the processor board by nesting in the same slot as the processor board. It attaches to two of the four processor nodes and allows two independent interfaces to each processor through interface circuitry to front panel I/O functions.
The VIM-2 format enables systems engineers to combine two different types of VIM interfaces on the same processor board, perhaps supporting an input function with one module and an output function with the other. Other VIM mezzanine form factors include the VIM-4 format. VIM-4 is a full-width board that covers all four processor sites, and connects them to all front-panel connectors.
Available VIM module functions include FPDP, RACEway, digital receivers, parallel TTL I/O, serial I/O, multi-channel A-D, and high-speed A-D converters. Each module takes advantage of VIM`s high-speed parallel or serial interfaces, whichever is most appropriate.
VIM Specification
The VIM specification has been evolving for nearly two years. Several Pentek customers have used it with `C6x boards to develop custom high-performance interfaces for complex or proprietary functions not available as standard commercial off-the-shelf products. Taking advantage of new quad `C6x processor architecture and its supporting hardware and software, offers a significant reduction in development effort and time to market for unique or unusual applications.
VIM, which is Pentek`s high-performance mezzanine of choice, was designed to support not only VMEbus but also Compact PCI form factors. Pentek leaders are promoting the official industry standardization of VIM.
Rodger Hosking is vice president of Pentek Inc. in Upper Saddle River, N.J. For more information, contact Pentek on the World Wide Web at www.pentek.com/vimspec.
