By John McHale
SUNNYVALE, Calif. — Experts at Actel Corp. claim they can significantly reduce radiation-induced single-event upsets (SEUs) in their field programmable gate arrays (FPGAs) by using an approach they call triple module redundancy, or TMR.
Actel leaders say they are using TMR in the company's next generation of FPGAs for space applications.
TMR provides embedded "majority voting" circuits in flip-flop cells that will enhance device reliability by providing high tolerance to SEUs, Actel officials claim. TMR is "hardwired" into the silicon design as an additional feature, and does not require use of the FPGA's programmable gates or embedded processor machine cycles to support majority voting in software macros.
"SEUs can't be stopped completely, but they can be mitigated through redundancy," says John Bendekovic, director of worldwide aerospace sales for Actel. Actel's TMR process uses three flip flop cells instead of one; if a cosmic ray flips one cell from zero to one, the others will still be at zero and discard the one, he explains.
The way to prevent SEUs is in the design of the circuit, not at the foundry, where resistance to total dose and prompt dose is accomplished, Bendekovic explains. Actel engineers help prevent SEUs through TMR, while also maintaining density, he claims.
Current TMR solutions for space applications are very complex hardware/software design interventions. They require engineers to "burn gates" using much of the silicon's circuitry to implement their own versions of a soft TMR function, or to burn embedded processor machine cycles in executing majority vote software macros, Actel officials say.
Actel experts are conducting radiation testing on Actel's silicon to prove the TMR implementation, with results expected by the end of the year, company officials say.
"Implementation of TMR in silicon for mitigation of SEU radiation effects is a major step forward in increasing system reliability for all types of risk-critical space and other radiation-intensive applications," says Bob Pecotich, manager of high-reliability marketing at Actel. "A repair service call to an orbiting satellite due to failure from radiation bombardment is just not practical. The addition of TMR in Actel devices will provide a dramatic improvement in reducing SEUs and, thus, improve overall system reliability."
Another benefit involves the ever-shrinking sizes of integrated circuits. "Actel's TMR will mitigate the effects of smaller process geometries, which tend to reduce SEU thresholds," says Esmat Hamdy, senior vice president of technology and operations at Actel. "We believe TMR is more likely to be successfully implemented using Actel's antifuse architecture than with an SRAM silicon structure. In fact, incompatibilities between TMR and SRAM silicon structures will make TMR difficult and very expensive to implement in SRAM technology."
Introduction of Actel's new high-reliability FPGA devices based on 0.25-micron antifuse silicon with the TMR architecture is expected late in the fourth quarter of 2000. In the meantime, system developers can prototype new high-reliability system designs using Actel's SX-A product family, a package- and pin-compatible commercial grade equivalent to the upcoming TMR-based high-reliability product family, Actel officials say.
For more information on Actel's Triple Modular Redundancy, contact John Bendekovic by phone at 703-801-6033, by fax at 703-406-9574, by mail at 10841 Monticello Drive, Great Falls, Va. 22066, by e-mail at [email protected], or on the World Wide Web at http: www.actel.com.
