By John McHale
OTTAWA — Experts at of Interactive Circuits & Systems (ICS) in Ottawa, Ontario, are designing the next generation of the Front Panel Data Port (FPDP) specification, dubbed FPDP II. The new spec will have a 400 megabyte-per-second sustained data transfer rate.
The other highlights of FPDP II are backward compatibility with the current FPDP standard and double-edged clocking, says Jon Jones, application engineering manager at ICS. Helping the increased data rate is a 50 MHz clock rate, he explains. It will also provide multiple links on a single board, Jones says.
The previous 160 megabyte-per-second sustained rate of the original FPDP specification often proves to be inadequate for today`s applications, ICS officials say. Therefore, ICS engineers and their FPDP partners — about 30 individual companies — have decided to increase the capability.
ICS officials are designing the FPDP II standard through the VME International Trade Association in Scottsdale, Ariz.
"The ANSI/VITA 17-1998 Front Panel Data Port standard adds a new dimension to the VMEbus architecture by providing a method of carrying out high-speed data transfers among VMEbus modules without the need for modifying standard backplane connections," says John Rynearson, technical director at VITA. "Standardization through the ANSI accredited VITA Standards Organization (VSO) means that FPDP supporters can create an industry wide interoperable market for FPDP based products."
FPDP II`s backward compatibility helps integrators design more robust and capable systems, while enabling them to use and upgrade old technology, ICS officials say.
FPDP is currently designed into the future Virginia class (NSSN) new attack submarine. Because of the backward compatibility feature of the new specification, upgrading the NSSN application and other existing systems to FPDP II will be easy, Jones says.
When analyzing FPDP, uncertain clock-related propagation delays are the weak link in speed enhancement, ICS officials say. Although designers have been able to speed up FPDP through the clock driver and buffer families only marginally, ICS officials explain.
The FPDP II interface`s transmit side has the same high drive and PECL clock to supply the cable clock for the original FPDP. Yet for the next generation, a PLL provides clocks to the output buffers and doubles the bus clock frequency, ICS officials claim.
Not only does this control clock skew, but it also doubles the frequency of the data clock. This technique improves control of bus so the bus clock itself can increase from 40 to 50 MHz. This results in a bandwidth of 400 megabytes per second, Jones says.
The same advantages are possible at the receive interface by de-skewing the incoming clock using a PLL. The required data setup and hold times approach those of the input buffers themselves — 2.0 nanoseconds and 1.5 nanoseconds respectively. The improvements come without any real increase in the cable bandwidth, ICS officials claim.
The ICS spec also provides an auto-detect feature that switches between the single and double-edged clock by assigning a dedicated pin on the cable.
ICS engineers are developing hardware to test FPDP II performance. They are considering a custom, single-chip implementation of the FPDP II interface, ICS officials say. For more information on FPDP II enter the World Wide Web at http://www.fpdp.com.
