By Mike Fleming of DSP Architectures Inc., in Vancouver, Wash.
Is the modern aerospace digital signal processor (DSP) a stand-alone solution with both CPU and DSP capability? Is it on the verge of getting sucked into the mainstream microprocessor's silicon? Or is it a separate device that complements the host microprocessor while maintaining a high degree of autonomy?
This is not the first time a stand-alone chip has faced the prospect of being permanently integrated into the systems' host microprocessor. Back in the 1980's, the Floating Point Unit (FPU) flourished as a stand-alone chip with what seemed like ever-increasing capabilities.
Most of us remember the Intel 8087 and its successive iterations, the 80287, 80387, etc. The functions, precision, and features seemed endless at the time. But the FPU reached a point where its functional progress ceased and its matured value to the majority of microprocessor customers warranted permanent integration into the CPU chip.
Over time its allocated percentage of the overall chip size shrank. Today, the Intel Pentium has less than 5 percent of its silicon area dedicated to the FPU. In contrast, the best example of a stand-alone chip that has so far defied integration into the microprocessor chip is the ever-evolving graphics processor (GP).
The GP services the visual needs of the end user. These needs are substantial to say the least; 33 percent of our brains are dedicated to just the control of our eyes.
But, daunting as it may be, the day that the GP matures to the degree that it can pump graphics and video as fast as we want, it too will get absorbed into the mainstream microprocessor's silicon real estate. The GP integration day, I believe, is just a few years off. It just makes sense to couple this major function more tightly at the chip level.
DSP chip heritage
The modern microprocessor is flexible enough to do many things well. It can add, subtract, multiply, integrate, differentiate, and correlate.
The initial seeds for the DSP chip came from the microprocessor. First there was the Intel 2920, and eventually the Texas Instruments TMS320. Designers derived these architectures directly from the popular microprocessors of their day; in fact, the TMS320 was just a "garden-variety" general-purpose microprocessor with a uni-bus architecture and a 16-bit multiplier thrown in.
Obviously, structures designed to process the needs of the business user cannot be expected to process digitized signals efficiently.
Digital signal processing is the business of extracting information from signals. These signals take many forms, i.e. real, complex, 1D, 2D, 3D, transient, and periodic. Signals are filtered, modulated, de-modulated, enhanced, encoded, decoded, compounded, compressed, de-compressed, and turned just about every way possible to communicate information efficiently.
At the heart of modern techniques that manage signals lies a subtle, yet supremely powerful operator — the time-to-frequency transform. And since real-world signals are hammered into sines and cosines by Mother Nature, the Fourier transform reigns as king.
The Fourier transform and its shortcut, the Fast Fourier Transform (FFT), are used extensively in powerful communication applications like ADSL and OFDM. The FFT is used in space applications to compress the massive amounts of image data satellites download to ground stations., and the FFT is the crown jewel of the system that produced the MRI image on your doctor's desk.
When Intel officials took note of the potential of the upstart DSP market back in the early 1990s, they complemented the Pentium with multi-media eXtentions (MMX). MMX was to lead the way for a massive "crossing over" of software engineers into the realm of signal and image processing.
Although there were some successes, like MPEG decoding, MMX, or anything like it has faded from Intel's promos. Additionally, Motorola blasted Altivec onto the media in a big way. Again, this barrage has faded drastically to the point where an Altivec search of the PowerPC press releases for the last two years yields almost nothing. These were terrific initial attempts at attempting to apply mainstream micros to the enticing world of image and signal processing.
The concept of a vector processor to perform digital signal processing is not new; we used to call them array processors many years ago. But the idea is the same; accelerate math and matrix operations by weeding out the structures that deal with scalar, decision logic, and strings.
Vector processors provide high-level operations that work on vectors — linear arrays of numbers. A Vector processor can function in general-purpose programming.
Motorola's Altivec attempts to implement the concept of doing DSP-type stuff with an on-chip vector processor that accelerates matrix and FFT calculations in concert with the microprocessor circuitry. Tightly coupled to the PowerPC and its peripherals, this enables fast concurrent processing of vector operands.
The G4 processor features a high-frequency super scalar PowerPC core, capable of issuing three instructions per clock cycle (two instructions + branch) into seven independent execution units.
In the G4 applications must be specially coded to take advantage of the vector processor, which allows them to perform certain mathematical operations very quickly. A vector processor executes the same operation on several different pieces of data at the same time.
In the G4, as many as eight simultaneous operations can execute in one clock cycle in the vector unit, which makes the G4 fast when working with math-intensive applications.
Enter the Frequency Domain
Implementing efficient FFT structures in the DSP chip silicon buys you a ticket into the mysterious and virtually untapped frequency domain, a domain of endless possibilities. These possibilities remind me of the electronics transition from analog to digital, a completely different way of solving technology problems.
Take for example the DSL modem that easily outperforms our 56 Kbaud dial-up modems many times over. The environment of that unshielded 10,000 foot (or even greater) copper pair of wires is messy at best; creates massive noise, strong dynamic interference, and a constantly changing response curve that almost defies measurement, let alone equalization.
But, once the incoming signal is transformed via the FFT into the frequency domain, the noise and interference is easily recognized: The lines response at that instant is quickly measured, and the very next signals to be used to transmit information are chosen to move away from the interference so as not to lose information. It is this "visibility" that comes from the frequency domain that makes it possible.
Just as with the graphics chip, the input and output for the vector processor, or the DSP, requires fast and plentiful dedicated I/O to keep up with signals in real time. Having a separate DSP or vector processor chip offloads the CPU from this task. A glowing inefficiency appears when the I/O is not balanced with the internal processing.
The Data Flow architecture addresses I/O and processing power balancing and is especially well suited for real time processing such as DSP.
NASA is addressing a DSP chip called the Radiation Hardened Vector Processor (RHVP) under its New Millennium Program. The RHVP uses a chip set called the RHDSP24 and its companion memory manager, the RHtMMU24. The RHVP functions as a separate chip co-processor to the radiation hardened PowerPC, with its own Input/Output to sustain fast, real time sample rates.
There is plenty of room to grow. Just like the graphics processor has many killer applications to address, the vector processor has to conquer 3-D virtual reality image processing — not just display, like the graphics processor, but actual recognition, filtering, artifact elimination, and rate reduction.
What will make the winning architecture successful? We ask this question, because it is not always obvious with many competing technologies such as MMX.
The aerospace DSP must do several things:
- be cheap enough;
- be highly independent of the main CPU, especially the I/O;
- be easy to use from assembler and high-level languages; and
- have the same sort of optimization rules as the rest of the processor architecture.
