By Keith Gurnett and Tom Adams
The term “three-dimensional integration” sounds as though it were simply another logical step in the miniaturization of devices and systems. In many instances, 3-D integration does involve miniaturization in the sense that the z-dimension of an assembly is reduced, but the real purpose of 3-D integration is higher speed and better performance, not merely shrinkage of the physical dimensions.
Achieving much higher speed is the goal of a development project at the Fraunhofer Institute IZM in Berlin, in cooperation with German companies like EADS (European Aeronautic Defence and Space Company) and Siemens. The goal of the project is to develop very high-bit-rate motherboards, raising the current speed of data throughput by as much as 40 gigabits per second. Siemens will use the new board in advanced switching equipment, while EADS will take advantage of it in defense applications
The integrated-circuit (IC) chips used are in a ball-grid array (BGA) format. No modification of the chip or of its solder ball interconnection to the board is in the works. Instead, development centers on optimizing speed by adding passives as near to the bond pads and the high-speed functional element on the board as is physically practical. Most will be decoupling capacitors, but some will be matching impedances, to boost the data bit rate of the system.
The capacitors need to be of the lowest inductance possible. Flat laminated plate structures, such as the surface-mount types, tend to be in this category and it is mainly the termination construction and the connecting path between the capacitor and the IC that adds the inductive element.
The Fraunhofer development team, headed by physicist Andreas Ostmann, will embed the capacitors in the printed wiring board directly under the bond pad. In this way, each bond pad can have its own decoupling capacitor, located in the most favorable spot.
Embedding active components
Finding a way to embed passive components follows naturally on the Fraunhofer Institute’s development of embedded active components. The method known as Chip-In-Polymer was worked out by Ostmann and his colleagues as part of a larger project called HIDING DIES conducted by a European consortium of research institutes and manufacturers.
The active components used in Chip-In-Polymer are first thinned to 50 microns, and sometimes even thinner. The board starts out as the core of a halogen-free variety of FR4 that also differs from conventional FR4 by having a higher glass transition temperature (Tg). The higher Tg will enable the finished board to pass through lead-free reflow without damage. Ultimately, though, one of the consequences of embedding both active and passive components may be the elimination of reflow altogether.
The core to which active components are attached is 100 to 500 microns thick, Ostmann reports. The aluminum bond pads on the die are covered by a copper bump for compatibility, and the thinned chips are placed onto a printed adhesive or die-attach film by conventional die-bond equipment. A critical parameter is the absolute flatness of the thinned chips.
A build-up layer, in the form of resin-coated copper (RCC) is then vacuum-laminated onto the board. The copper is 8 microns thick, while the resin is 80 microns thick. A laser drills microvias down to the copper-bump bond pads on the active chip, and the microvias are plated with copper.
Printed or discrete?
An early decision facing Ostmann’s team was whether to embed discrete capacitors and resistors-including standard surface-mount technology capacitors and resistors-or whether to use printed resistor/capacitor material. One of the critical parameters in embedding components is that the surface of the board above the embedded components must be perfectly flat.
Printed resistor materials or the similar capacitive planes would be the thinnest possible choice. In some applications, these would be the perfect choice. “You have one area of the PCB where a capacitive layer or a resistive layer is structured,” Ostmann explains. “It’s great because then with one process you have a more or less infinite number of components.”
A quick look at the project’s specifications, however, revealed that the tolerances of printed resistors were too low. “When we talked about the requirements, we also talked about integrated resistors, meaning that you have a resistive layer, and by structuring that layer you get a high number of resistors. But the issue was always that tolerances are not sufficient, so then you have to go to laser trimming, which increases the cost again,” Ostmann explains. “The second thing is that the range of resistance they can achieve is not sufficient.”
A problem of height
The project will therefore employ discrete passive components. Since discretes can easily provide the range of values needed for the project, the question becomes: how can they be assembled? Can conventional surface-mount components be used?
The key parameter is the height of the component compared to the thickness of the RCC layer. When received at Fraunhofer, the board will consist of inner layers and the inner core. “Just one outer layer will be missing on the bottom and on the top,” Ostmann says. His team will add the passive components, and then laminate the top layer. The passive components need to be short enough-or the RCC layer needs to be thick enough-to permit the top surface to come out flat.
There is considerable incentive to use conventional surface-mount passive components, not only because they are cheaper than any other available discrete passives, but also because their successful use would serve as a good design model for others to follow. There is a thickness problem, though. The RCC layer is 80 to 90 microns thick, while the smallest surface-mount capacitors-0201s and 01005s-are between 200 and 300 microns thick.
Specialized discrete capacitors are available. “One of our partners has already received capacitors of 30 micron thickness from a Japanese company,” Ostmann notes. Furthermore, the 30-micron capacitors have copper terminations, a necessity for this project. But these are not standard items. “We get them on an experimental or prototype bases,” he says. “You cannot go to the catalogue and buy them today.”
A thicker overlay?
It is too soon to tell which of the available discrete components, ranging from 30 to 200 microns in height, will be used. If the standard 80-micron RCC layer is used, nearly all of these components will be too tall.
One solution is to use a thicker build-up layer to accommodate the thicker passives. “One suppler in Europe was willing to supply us with extremely thick RCC, which is not a volume product, but on an experimental basis,” Ostmann notes. “The thickest they can achieve is up to 150 microns.”
The advantage of the RCC material is that it contains no fibers, just resin and filler particles. When it is laminated onto a component, the resin and the filler particles can flow laterally, so that the component makes a dent in the bottom side of the material without causing a bump on the top side. But the 150 micron thickness limit might be too small for some tall components.”
Another possibility is to use prepreg-the same material that builds up FR4 boards. Prepreg differs from RCC in that it contains woven glass fibers to stabilize the resin in its uncured state and to stabilize and reduce the mechanical properties such as its CTE. If prepreg is laminated down onto a component, the resin will tend to flow laterally, but the woven glass doesn’t move, and the end result is an unacceptable bump at the surface.
But prepreg is inexpensive, and thick enough for the tallest passive components that Ostmann is likely to use-if you cut or punch holes in the prepreg. Ostmann has already tried prepreg, not with passive components, but with larger active components thinned down to the critical 200-micron thickness. “The thick component, 200 microns, was nicely embedded in the prepreg using this approach with laser-cut holes.”
If prepreg with a relatively high proportion of resin is used, this process is very forgiving, Ostmann has found. He punches a hole larger than the component, leaving a space of 50 microns or even more around the edge of the component. During lamination the resin simply flows into the space and effectively encapsulates the component. The greater tolerance simplifies placement of the laminate.
There is no consensus yet on the best way to make the holes in the prepreg. Ostmann used an ultraviolet laser-effective, but rather slow and expensive. A different laser might bring costs down. Punching out the holes mechanically might work.
Putting the pieces together
From all of the possibilities-specialty passive components, standard SMT passive components, specialty RCC, standard prepreg-Ostmann and his team will find the best combination for achieving the end-users’ requirements in the project. Along the way they will demonstrate the feasibility not only of the technologies that they end up using, but of other technologies that may be a perfect fit in another application.
In another task of the project, the German company Isola is working with nanoparticles to develop superior laminate materials. The hope is that nanofilled layers will improve the CTE capability of the laminate as well as the thermal conductivity and the RF properties. Using nanoparticles should permit higher filler content and lower the dielectric constant of the laminate, which will reduce the electrical losses that impede the speed. This in turn should reduce the value of the capacitive component required.
Military interest in embedded components, both active and passive, is partly focused on the presumably superior protection from shock and vibration that embedding provides. But the real drive is from size, speed, and weight. Meanwhile, industry-wide interest in the embedding of passive components is growing. Both Mentor Graphics and Cadence Design Systems have recently offered software that automates the design process for embedded passive components for the existing sheet forms of resistors and capacitors. The Fraunhofer project, by using embedded passives to boost performance and save space, may give impetus to further developments.
