By Keith Gurnett and Tom Adams
The process of embedding integrated circuits (ICs) within the printed circuit board is often described as the next logical step in the overall miniaturization of electronics systems. Instead of surface-mounting ICs on top of the board, they are in some fashion (there are at least two different approaches) contained within the board itself. Embedding chips has two general advantages: higher potential function density and higher transmission speeds. Since it extends the x-y miniaturization of components into the z dimension, the embedding of chips has been described as 3-dimensional integration of components.
Embedded chips also promise to revolutionize the processes of component packaging and attachment. They are in one sense a new breed of “package,” but they are neither wire-bonded packages nor flip chips. They also can comply with lead-free regulations without regard to high reflow temperatures because they make reflow unnecessary.
Efforts to develop chips that are embedded within a printed circuit board-with the goal of making production at reasonable cost a reality-are in progress at several centers. A European consortium is cooperating in what is called the HIDING DIES project (www.hidingdies.net). Its work is based on the so-called “Chip in Polymer” concept, jointly developed by Fraunhofer IZM and Technical University of Berlin.
Partners in the project include Nokia (Finland), Philips (Netherlands), AT&S (Austria), Datacon (Austria), CWM (Germany), IMEC (Belgium), and the Technical University of Berlin (Germany). At least one embedded-chip product has already reached consumer markets, and others are likely to follow shortly.
The term “embedded” has two slightly different meanings. In the HIDING DIES project, the chip is attached to a board, and subsequently covered with a suitable epoxy layer. At Imbera, a cavity is cut into the board, the chip is placed into the cavity, and finally covered by an epoxy layer.
There are as yet no distinctly military or aerospace applications for embedded chips, but the advantages that these structures provide are so compelling that their use in military applications-which may at least initially involve the use in military or aerospace applications of embedded chips designed for consumer applications-seems inevitable within a few years.
Current state of development
The board used is a double-layered core made from a halogen-free FR4 material. Because of the European Restriction of Hazardous Substances (RoHS) requirements, all materials used in development were free from bromine, lead, and other materials that will be banned as of July 1. Core thickness ranges from 1.5 to 0.1 millimeters; many cores used during development were 0.5 millimeters thick. An important detail of this FR4 material is its glass transition temperature (Tg) of 170°C -far above the Tg of 140°C of conventional brominated FR4. The higher Tg is needed because the assembly is designed to survive lead-free reflow temperatures.
Designers back-thin the wafers to be used down to 50 microns, and in some cases thinner. They cover the aluminum contact pads on the chips with copper bumps to make them compatible with printed circuit board metallization processes. Currently, the pads are sputtered with 0.2 microns of T/W/Cu, structured by a lithography step, and reinforced by electroless deposition of 5 microns of copper. Future plans call for the development of a purely electroless copper bumping process to reduce costs.
Next, engineers die bond the singulated chips to the board using conventional die-bond equipment to conform with the requirement that production processes should maintain low costs. They use printed adhesive or die attach film, and pay special attention even to thickness of the bond line to avoid irregularities in the dielectric that will later be built up on the chip.
Designers then vacuum-laminate high-Tg resin-coated copper (RCC) into both sides of the core. The RCC dielectric thickness is 70 microns, and the copper thickness 5 microns. Then they drill microvias to provide access to the bond pads on the chip, and plate the microvias with printed circuit board-compatible copper.
Characteristics of embedded modules
Andreas Ostmann, physicist at Fraunhofer IZM, notes that the final product is somewhat similar to a chip-on-board (COB) construction. “Like a COB, the embedded chip is die-bonded onto an FR4 substrate. The epoxy used on top of the embedded chip is an epoxy, similar to the glop top used on COBs. But where a COB has wire bonds, the embedded chip has microvias-along with a greater degree of miniaturization and faster transmission speeds.”
As with any package, one of the chief concerns is thermal effects on materials that have varying coefficients of thermal expansion-and particularly about expansion in the z dimension at high temperatures. The CTE of the silicon chip is about 3, while the CTE of the advanced FR4 material is 12 to 13 in the x-y axes, and about 25 in the z axis.
“We have developed some processing tricks, and by using those tricks we have found that after lamination of the epoxy on top of the chip there is a maximum bending during thermal stressing of 10 microns, which is acceptable,” Ostmann says. “Without the processing tricks, we would have bending of 60 to 70 microns, which would be unacceptable.
“We have taken the embedded chip up to 150 degrees Celsius and down to -55°C in simulation, and what we have seen is that the whole thing starts to move and to bow, just as a printed circuit board with a flip chip would do, because flip chips also move at high temperatures. But the samples remain stable, because the chip is embedded from all sides.”
Ostmann points out that the development process necessarily investigated many combinations of materials and their thermal interactions. One test involved laminating an 8-inch wafer of 50-micron thickness onto a 100-micron thick FR4 printed circuit board. Surprisingly, the bonded wafer survived this procedure without breaking.
One of the problems in developing embedded chips involved the thinness of the copper interconnects, which initially were too weak. Making the interconnects more robust solved the problem, and current production samples have endured 1,000 hours of humidity testing without failing.
Another material constraint is the relatively high dielectric losses involved with FR4 epoxies. As signal frequencies increase, Ostmann estimates that the various FR4 materials will reach a useful limit at around 5 GHz-one reason that Ostmann’s team has begun to investigate build-up materials having much lower dielectric losses. One of the alternatives is a build-up material with BCB instead of epoxy, but this material costs significantly more than a similar FR4 epoxy. Overall, of course, conventional FR4 offers an “economy of scale” which will persist for a long while.
Designs and applications
What might a product using embedded chips look like? “It’s inherently a bit more expensive than conventional printed circuit board, because you have to put it through a die-bond process, and you need fine lines and spaces, so the cost is somewhat higher. So the modules will always be kept as small as possible,” Ostmann notes. Putting 20 embedded chips into one module, he says, would be impractical. The problem, of course, is yield, and modules using four or more die may benefit from the use of Known Good Die (KGD).
A module using two or three chips, a few 1000pf capacitors, and a few low-resistance resistors would probably be a reasonable design. Such a design would make good use of 3-D miniaturization, have reasonable production costs, and take advantage of high signal frequencies. One potential application: navigation systems, especially for relatively small missiles or ordnance, where high processing speed in a digital signal processor, low weight, and low cost are important factors. Autopilots and some radar systems are also good candidates.
It is possible to surface-mount conventional resistors and capacitors on top of the embedded chip, Ostmann observes, and his team has used this approach, and even had surface-mounted resistors and capacitors survive lead-free reflow temperatures. “But there are still questions about the reliability of this approach. Besides, if I have only one routing layer above the chip, there might not be enough space to put capacitors above the chip.”
A more likely approach would be to use embeddable resistors and capacitors, even though these generally have more modest parametric values. They are also more costly than the conventional SM types. One striking advantage: the whole process of reflow, and especially the difficult 260°C lead-free reflow, becomes unnecessary for these modules if there are no surface-mounted items. Ostmann does not anticipate that moisture sensitivity levels for embedded chip modules will be significantly different from current production parameters, even though new materials may be used.
Ostmann points out that the thinned die used in their work are typically 10 by 10 mm; some are 5 by 5 mm. Pitch in both sizes is 200 microns. Although the his group has worked with much larger die-including the successful mounting of flip chips measuring 40 by 40 millimeters-he sees no advantages in embedding die having very large areas.
Although he has no test data to refer to, Ostmann says he believes embedded-chip modules will be extremely resistant to shock and vibration. Nokia, for example, is very interested in the embedded die concept, because people frequently drop their cell phones. Conventional surface-mounted printed circuit boards have their components on the surface, where they are more vulnerable to g forces. Ostmann says that embedding the silicon within the board gives embedded designs much greater survivability.
Embedded chips can offer excellent shielding, without the need to put an external metal lid over the chip or over the circuit. “You can put a complete copper layer over the embedded chip and it is totally electrically sealed inside,” Ostmann says.
To date, development has focused on embedding chips only on one side of the board. Ostmann notes that the result is a module that is inherently asymmetrical. One possible solution: to put build-up material, but no chips, on the other side of the board.
The HIDING DIES project has one more year to run, and Ostmann expects to investigate several assembly options. One possibility: using a new nonwoven fiber material for reinforcement. The consortium will also experiment with the embedding of a stack of two or more chips-feasible because each die is at most 50 microns thick. They will also look into making core-less packages.
At Imbera Electronics in Finland, development of board-embedded chip technology has taken a slightly different route. Imbera calls its product an Integrated Module Board, or IMB. Imbera’s manufacturing at an Aspocomp Salo plant uses HDI printed-circuit-board manufacturing processes that have been optimized.
Unlike the Fraunhofer die, which is thinned to 50 microns or less, Imbera uses an unthinned die, and thus avoids the cost of thinning the silicon. The IC components are embedded inside the printed circuit board core layer during the core manufacturing process and are connected directly to the core layer copper foil. Microvias are then drilled with a UV laser, and metallized using a semi-additive process with pattern plating process.
Both approaches can include embedded passive components between the board layers. Several companies are currently developing thin-film capacitors and resistors for just this purpose. Alternately, passives can be printed directly onto the printed circuit board material inside one of the layers.
