Field-programmable gate arrays are becoming the choice of systems designers over their longtime preference of digital signal processing hardware.
By John McHale
The last evolution in digital signal processing for military systems was the release of the PowerPC Altivec chip, which enabled general-purpose processors to perform functions that before only specialized DSP chips, such as those designed by Analog Devices and Texas Instruments (TI), could provide.
Today military systems designers are meeting demands for ever-greater DSP performance with reconfigurable field programmable gate arrays (FPGAs). Engineers love the flexibility and power efficiency that FPGAs give them.
FPGAs are the commercial off-the-shelf (COTS) solution for the increased performance demands of military signal-processing applications, says Manuel Uhm, senior marketing manager, DSP Division at Xilinx in San Jose, Calif. Their flexibility, power efficiency, and performance capabilities are what make prime contractors spend millions on them for radar systems, software-defined radio applications, and even anti-improvised explosive device (IED) solutions, which require quick turnaround times.
Regarding software-defined radio, FPGAs fit right into the SCA (Software Communications Architecture) framework on which SDR is based for the U.S. Army’s Joint Tactical Radio System, Uhm says.
Multicore processors are going parallel to make them faster, “while we’ve been playing the parallel game for years,” Uhm says. FPGAs have the guaranteed determinism and latency necessary for high-performance signal processing with a much lower degree of risk, he adds. The work of multiple processors can be accomplished on one FPGA, Uhm notes.
“The fact that customers are increasingly turning to COTS vendors for their FPGA processing platform needs is a trend unto itself,” says Mark Littlefield, manager of application engineering products at Curtiss-Wright Controls Embedded Computing in Leesburg, Va. “Traditionally, the FPGA portion of a system was developed in-house even if the rest of the system was COTS-based. This is rapidly changing. However, COTS vendors have to provide significant value beyond a [box of parts]; they need to supply rich tool kits, including both FPGA IP and software, to enable their customers to get their designs running and fielded as quickly as possible. Our customers are feeling increasing pressure to shorten their design cycles and are turning to us to help them achieve that.”
It is difficult to use FPGAs, says Jeff Milrod, president of BittWare in Concord, N.H. If the Analog Devices Tigersharc DSP chip or TI’s 64 series could be programmed as easily in C as general-purpose processors, everyone would be happy, he adds.
The problem is that demand has outstripped capability, Milrod says. “It has kind of followed Moore’s Law, with performance demand growing much faster than performance capability.”
Customers are demanding more and more FPGAs, especially in radar and signals intelligence applications, says Rodger Hosking, vice president at Pentek Inc. in Upper Saddle River, N.J. FPGAs get involved as early as possible in the signal processing food chain, such as in analog-to-digital conversion, he says.
Pentek has embraced the Xilinx product line because it has worked for its customers, but Altera in San Jose, Calif., makes a solid product as well, Hosking says. The two companies often flip-flop each other in technology advancements, he adds.
BittWare uses Stratix FPGAs from Altera, finding them power-efficient with excellent development tools, Milrod says.
“The other trend is our market’s insatiable appetite for larger/faster processors and lower power consumption,” Littlefield says. “Processing density in the form of mega-ops per watt still dominates the mil-aero COTS market. FPGAs are interesting in that the power they consume is directly related to the bitstream loaded into them and the resources that the bitstream uses. However, customers are beginning to look for both processor and board-level features to help them better manage their power consumption.
“While Curtiss-Wright uses FPGAs on nearly all of the DSP (and other processing and I/O) boards to add utility functions, my specific product line is focused on user-programmable FPGA processing nodes,” Littlefield continues. “Our customers use these FPGA nodes in a number of ways, but most involve DSP operations.
“Typically this processing is the first step following data acquisition-digital down-conversion, filtering, and so on,” Littlefield continues. “Data streams in [typically via the high-speed serial ports], is then processed in the FPGA, and after which it is sent on to more traditional microprocessors for later processing stages.
“The needs and wants of FPGA-based customers are somewhat more varied than those of more traditional single-board or processor-based DSP customers,” Littlefield says. “This is because FPGA-based COTS products are relatively new to the market compared to these other products. Having said that, there are a few common features that all customers look for,” Littlefield says: “standard” form factor-6U/3U VME or VPX, PMC/XMC, etc.; I/O directly to the FPGA, either in the form of multiple LVDS/LVTTL or high-speed serial (and often both); attached memories, although the flavor of memories-SDRAM, DDR2 SRAM, or QDR2 SRAM-are often different for different customers; and some sort of connectivity to later processing stages-bus, serial switching fabric, etc.
FPGA development tools
FPGAs are getting easier to program, but slowly, Littlefield says. “There are numerous design paths available to today’s developer. Most continue to use a traditional VHDL or Verilog-based tool chain but are increasingly turning to tools such as Xilinx EDK to help automate some of that development. In addition, other, more novel tool chains such as SystemC and Simulink/SystemGenerator are of increasing interest to our customers.
“Our customers express increasing frustration with development tools and methodologies available for FPGA development and the need for specialized (and often very expensive) development talent,” says Littlefield. “They are looking for ways to leverage the power of FPGAs without the pain that is usually associated with it.
“The tool kits provided with Curtiss-Wright’s FPGA-based products all use Xilinx EDK as our primary-supported tool chain, along with Mentor’s ModelSim for simulation,” Littlefield continues. “Our IP blocks are developed using these same tools. Having said that, we recognize that customers often have their own, particular set of tools that they use for FPGA development and we try to accommodate that. The Simulink/SystemGenerator toolchain is of growing interest to our customers and while we document and support that tool chain in our development kit, we are looking at ways to make it better/easier to develop applications for our products with it.”
Pentek uses tools such as Simulink and Matlab to code in VHDL, Hosking says. Tools such as those from Celoxica will provide a quick turnaround in development time, but only for what Hosking calls higher-level applications, not those necessary for mission-critical military applications.
Xilinx has a wizard tool that functions on the middle level, but Pentek’s military customers need functionality at a much more detailed, lower level, Hosking says.
MATLAB and other modeling tools enable that type of design, especially the new modeling capability that allows engineers to simulate FPGA designs before programming them in VHDL, Hosking says. These simulation tools save hours and hours of development time, he adds.
With the release of version 9.2 of the AccelDSP synthesis tool and System Generator for DSP, the development-tool component of the Xilinx XtremeDSP solution provides higher levels of performance and tighter integration between the two tools to simplify the FPGA design flow for developers who use the MATLAB and Simulink modeling environments concurrently.
“DSP-optimized FPGAs such as the Spartan-3A DSP family and Virtex-5 platform FPGAs are quickly being adopted into new and emerging markets by design teams without traditional FPGA design expertise,” says Tom Feist, marketing director for Xilinx embedded and signal processing solutions. “The System Generator for DSP and AccelDSP tools enable design teams to quickly assess the performance, cost, and power benefits of an FPGA-based implementation for their unique applications, and to develop final implementations that leverage the FPGA device resources using tools and languages familiar to algorithm and system-level designers.”
Using System Generator for DSP, developers of multirate DSP designs, typical of wireless and defense applications, will see as much as a 38 percent improvement in Fmax performance when using version 9.2 with no modification to existing designs. A new mapping algorithm has been implemented that uses register duplication and placement based on recursive partitioning of loads on high fanout nets typical of multirate designs, Xilinx officials say. This and other enhancements deliver the ease of use, levels of abstraction, and quality of results demanded by designers new to FPGAs who are increasingly selecting programmable logic as their hardware platform of choice.
“Until two years ago, surveys showed that maximum MIPS were always the top criteria in a development team’s choice of chip to use in a DSP application,” says Will Strauss, president of Forward Concepts, a DSP market research firm in Tempe, Ariz. “But with today’s increasing chip complexity and time-to-market pressures, development tools are now the key item for chip selection, and Xilinx is taking a leadership role in addressing designer needs.”
The System Generator for DSP tool, AccelDSP synthesis tool, and a set of DSP intellectual-property cores are the main components of the XtremeDSP design environment for implementing DSP designs developed in MATLAB and Simulink software into Xilinx FPGAs. Unlike disjointed design flows which require separate algorithm development and RTL coding steps, System Generator for DSP provides an integrated modeling and verification environment that enables a smooth path from initial design capture in Simulink to FPGA design closure, without the need to learn or use traditional RTL design methodologies, Xilinx officials say. The AccelDSP synthesis tool is a high-level MATLAB language-based tool for designing DSP blocks for Xilinx FPGAs that automates floating- to fixed-point conversion, generates synthesizable VHDL or Verilog, and creates a test bench for verification. Designers can generate a fixed-point C++ model or System Generator block from a MATLAB algorithm.
Programming in hardware is much less risky than programming in software, Uhm says. Software has too many variables; something will blow up or a bizarre bug that no one thought of may cause the system to crash, Uhm says. The VHDL debug tools are much more efficient.
It is hard to program in VHDL, Uhm says, but systems integrators or companies involved in FPGA design have “VHDL jocks” on staff and get the job done. The more people who use FPGAs, the easier it will become to program them, Milrod says.
Milrod says he and his team at BittWare would like to design a framework “that provides validated board-level interfaces for I/O, communications, and memory; an internal dataflow interconnect fabric that allows the framework modules to be easily connected; and a control fabric that allows them to be easily coordinated and controlled. When properly implemented, an FPGA framework creates a stable, high-performance signal processing platform that, as COTS intended, frees the user to focus on application development rather than reinventing board-level infrastructure. “Why should every customer have to re-do it?,” he asks.
FPGA applications
“There are two basic classes of applications for which our products are being applied-front-end DSP (radar, SIGINT, etc.) and image processing,” Curtiss-Wright’s Littlefield says. “In the DSP domain, there is often some sort of data decimation done so that the amount of data coming out of the FPGA is much less than that going in.
“An interesting application of FPGAs that has yet to take hold in the mil-aero space is to use FPGAs as algorithm accelerators,” Littlefield continues. “There has been some very interesting work done in the academic community using FPGAs to accelerate various stages of DSP processing [and thus potentially reduce the size and power consumption of a system]. However, this hasn’t yet shown up in the mil-aero community-probably because the COTS vendors haven’t yet provided adequate tools and infrastructure to make it easy to design and build such a system. Addressing this application will be a focus for Curtiss-Wright in the not-too-distant future.”
FPGA offerings
Curtiss-Wright’s 6U CHAMP-FX2 board, its first FPGA-based VPX-REDI (VITA 46/48) compute engine, combines the flexibility of Xilinx FPGA-based reconfigurable computing, high-performance Power Architecture (PowerPC) processing, and the high bandwidth of serial switched fabrics provided by the new VPX standards. The board features dual high-performance Xilinx Virtex-5 LXT FPGAs and an AltiVec-enabled dual-core Freescale 8641 PowerPC processor in a heterogeneous FPGA/CPU design.
BittWare’s GT-3U-cPCI is a ruggedized 3U CompactPCI board designed for demanding multiprocessor applications. The GT3U features a large Altera Stratix II GX FPGA, one cluster of four ADSP-TS201S TigerSHARC processors from Analog Devices, a front-panel interface supplying four channels of high-speed SerDes tranceivers, and a back-panel interface providing RS232/RS422 and 10/100 Ethernet. Simultaneous on-board and off-board data transfers can be achieved at a rate of 2 gigabits per second via BittWare’s ATLANTiS framework employed in the Stratix II GX FPGA.
At the heart of the GT3U is an Altera Stratix II GX FPGA containing 90,960 equivalent LEs, 4.5 megabits of RAM, 192 embedded 18 by 18 multipliers, 48 DSP blocks, and 8 PLLs. The FPGA provides pre-, post-, or co-processing to complement the TigerSHARC processing cluster, while enabling routing of the TigerSHARC I/O at a rate of more than 2 gigabits per second via BittWare’s ATLANTiS framework.
Pentek offers the Model 7142 multichannel, high-speed data converter suitable for connection to the HF or IF ports of a communications system. It includes four A/Ds and one upconverter and D/A converter capable of bandwidths as fast as 50 MHz. The Model 7142 uses the PMC format and supports the emerging VITA 42 XMC standard for switched fabric interfaces. The front end accepts four full-scale analog HF or IF inputs on front-panel MMCX connectors at +10 dBm into 50 ohms with transformer coupling into Linear Technology LTC2255 14-bit 125 MHz A/D converters. The digital outputs are delivered into the Virtex-4 FPGA for signal processing or for routing to other module resources.
The Model 7142 architecture includes two Virtex-4 FPGAs. All the board’s data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering, and SDRAM memory control. In addition to the built-in functions, users can include custom IP for data processing.
A TI DAC5686 digital upconverter (DUC) and D/A accepts a baseband real or complex data stream from the FPGA with signal bandwidths as fast as 40 MHz. When operating as an upconverter, it interpolates and translates real or complex baseband input signals to any IF center frequency between DC and 160 MHz.
VMETRO released its Phoenix VPF2, a rugged COTS DSP card that integrates a Freescale MPC8641D processor, two Xilinx Virtex-5 FPGAs, and a VXS-based high-speed serial interconnect fabric. Closely coupled to the MPC8641D processor are two Xilinx Virtex-5 SX95T or LX110T FPGAs. With on-chip serial transceivers, the Virtex-5 FPGA options provide high-bandwidth, off-board serial communications channels to processing and I/O subsystems.
“The Phoenix VPF2 is two processing platforms in one. The result is a scalable processing engine able to tackle a range of demanding applications,” says Thomas Nygaard, chief technical officer, VMETRO.
TEK Microsystems Inc. of Chelmsford, Mass., unveiled its Serial FPDP core with support for Xilinx’s Virtex-5 FPGAs. “A benefit of FPGA-based products with well-designed IP support is the ability to migrate to newer, higher-performance devices without redesigning the application,” says Andy Reddig, Tekmicro’s president and chief technology officer. “The Serial FPDP core implements an open-standard interface, allowing customers to use a common, modular component across a range of form factors, products, and technology.”
Xilinx adds greater power efficiency to Spartan-3A DSP platform FPGAs
Xilinx, in San Jose, Calif., announced the addition of power-efficient Spartan-3A DSP devices to its XtremeDSP portfolio of solutions for signal processing applications. The new devices, which are in production today, deliver high-performance DSP capabilities in a low-power FPGA for applications such as tactical radios for military communications, wireless access points, and portable medical equipment.
The Spartan-3A DSP low-power (LP) devices deliver a 50 percent static power savings, and a 70 percent savings while in suspend mode, compared to standard devices, and are available in industrial rated grades, Xilinx officials say. The lower power complements the dynamic power advantage inherent in the Spartan-DSP series due to the integration of dedicated DSP circuitry.
“As the insatiable need for DSP performance increases in a plethora of applications, optimized energy efficiency becomes a requirement in many of those applications,” says Bruce Weyer, senior director of marketing for Xilinx’s Processing Solutions Group. “Applications that require significant DSP performance can now also benefit from the new power-efficiency/performance ratio Xilinx delivers with the addition of low-power Spartan DSP devices to the XtremeDSP portfolio.”
DSP power efficiency refers to the amount of power consumed performing signal-processing calculations. DSP power-efficiency measurements can be applied to systems, functions, building blocks, and common operations. The Spartan-3A DSP LP devices deliver 4.06 GMACs per mW at a speed of 250 Mhz in the lowest cost speed grade when analyzing the common multiply-and-accumulate operation.
The Spartan-3A DSP FPGA platform’s ability to perform signal processing functions without the need to consume logic resources enables designers to meet their performance and cost goals, while enabling better power efficiency. The XtremeDSP DSP48A slices that make up the dedicated DSP circuitry include dedicated 18 by 18 multipliers along with 18-bit pre-adder and 48-bit post-adder/accumulator to deliver performance of DSP functions at a low cost, company officials say.
Power efficiency can also be derived from the advanced static power-management suspend mode feature in the Spartan-3A DSP FPGA platform, which reduces FPGA power consumption while retaining the FPGA’s configuration data and maintaining the application state. This means devices can quickly enter and exit suspend mode as required.
The Spartan-3A DSP LP devices can be used in applications such as ultra portable ultrasound equipment, where digital beamforming is a key DSP application and channel counts vary from 16 to 128 depending on system requirements. The suspend mode capabilities of the Spartan-3A DSP FPGA platform also helps to extend battery life in these applications. Other applications that can benefit from the industry’s lowest-power/high-performance FPGA platform include MILCOM portable and mobile tactical radios, and portable night-vision equipment.
Altera unveils plug-and-play signal integrity technology
Altera Corp. in San Jose, Calif., announced its plug-and-play signal integrity technology, a system solution that is enabled by the latest Quartus II design software and is available now in production Stratix II GX field-programmable gate arrays (FPGAs). Plug-and-play signal integrity redefines FPGA use in high-performance systems by enabling a single-card configuration to be plugged into any designated system slot while under system power, company officials say.
Altera’s plug-and-play signal integrity technology is a combination of low-power linear adaptive equalization technology-Altera’s new Adaptive Dispersion Compensation Engine (ADCE)-and the hot-socketing capability found in every Altera FPGA. When hot-swapping a single-card configuration in a system, the ADCE automatically monitors and adjusts itself for interconnect loss and environmental variations.
“Our FPGAs’ ability to plug into a powered system and automatically adjust to varying system and environmental conditions allows our customers to reduce inventories, simplify maintenance procedures, and shorten time to market. The ADCE itself significantly reduces the tedious characterization effort that is the result of high-speed systems having varying link characteristics across card slots,” says Danny Biran, senior vice president of product and corporate marketing at Altera.
Plug-and-play signal integrity provides designers and system architects with production-qualified, hot-socketable Stratix II GX FPGAs that can actively monitor and automatically compensate for signal degradation in multigigabit system interconnects due to manufacturing, voltage, temperature, and design variations. Altera’s solution continuously adjusts equalizer settings for each of as many as 20 receivers found in the Stratix II GX FPGA family to provide the best eye opening for non-return-to-zero (NRZ) signals operating between 2.5 and 6.375 gigabits per second, improving system reliability, performance, and bit error rate (BER), Altera officials say.
