Air Force, NASA to develop radiation-hardened ARM processor for space

U.S. government space researchers want industry to develop a next-generation, radiation-hardened, general-purpose, multi-core processor within the next four years to meet on-board computing needs of future manned spacecraft and space robots.

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GREENBELT, Md. - U.S. government space researchers want industry to develop a next-generation, radiation-hardened, general-purpose, multi-core processor within the next four years to meet on-board computing needs of future manned spacecraft and space robots.

Officials of the NASA Goddard Space Flight Center in Greenbelt, Md., have issued the final solicitation for the High Performance Spaceflight Computing (HPSC) Processor Chiplet program for NASA and U.S. Air Force manned and unmanned spacecraft.

NASA and the U.S. Air Force are asking industry to develop a new rad-hard ARM processor for future space applications.

This four-year project is expected to deliver a next-generation, rad-hard space processor based on the ARM processor architecture to provide optimal power-to-performance for upgradeability, software availability, ease of use, and cost.

The HPSC project also will use Radiation Hard By Design (RHBD) standard cell libraries, as well as the ARM A53 processor with its internal NEON single instruction, multiple data (SIMD) design. Experts say a heterogeneous multi-core architecture using many different processor core types will not provide the best possible return on investment.

Applications for the HPSC processor will include military surveillance and weapons systems, human-rated spacecraft, habitats and vehicles, and robotic science and exploration platforms. System applications range from small satellites to large flagship-class missions.

Space computing tasks of the HPSC processor will include command and data handling, guidance navigation and control, and communications like software-defined radio; human assist, data representation, and cloud computing; high-rate, real-time sensor data processing; and autonomy and science processing.

The HPSC processor will include Serial RapidIO (SRIO) for high-bandwidth communications, and several interfaces to high-speed, off-chip memory. The SRIO interfaces also can function as advanced microcontroller bus architecture (AMBA)-bus bridges to tile or cascade several processors to increase bandwidth or improve fault tolerance.

The SRIO interface also can extend the HPSC processor to other SRIO-enabled processing devices such as field-programmable gate arrays (FPGAs), graphics processing units (GPUs), and in the future to other application-specific integrated circuit (ASIC)-based coprocessors.

Future onboard space computers for manned and unmanned missions will require big improvements in vision-based algorithms with real-time requirements; model-based reasoning techniques for autonomy; and high-rate instrument data processing.

A key goal for the HPSC project is the ability to trade dynamically between processing throughput, power consumption, and fault tolerance. The HPSC processor architecture sometimes will be inside a dedicated spaceflight computer, and sometimes may be embedded in a science instrument or spaceflight subsystem.

Companies interested were asked to submit bids by 20 July 2016.

E-mail NASA's Denise Sydnor FOR MORE INFORMATION at denise.y.sydnor@nasa.gov. Program details are online at www.fbo.gov/notices/eefe806f639ae00527a13da6b73b3001.

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