Xilinx FPGA-based VME and VXS-based embedded computer for digital signal processing introduced by Tekmicro

CHELMSFORD, Mass., 27 June 2011. TEK Microsystems Inc. in Chelmsford, Mass., is introducing the QuiXilica Aries-V6 embedded computer that combines 10 16-bit 250 megasample-per-second signals acquisition with Virtex 6 field-programmable gate array (FPGA) processing for 6U VME and VXS based applications. The board has 10 fast 16-bit resolution A/D converters with three Virtex-6 FPGAs, and can enable systems with as many as 180 coherent channels and 130 TeraMAC per second of processing in one chassis.

Jun 27th, 2011
Pennwell web 420 333
CHELMSFORD, Mass., 27 June 2011. TEK Microsystems Inc. in Chelmsford, Mass., is introducing the QuiXilica Aries-V6 single-board computer that combines 10 16-bit 250 megasample-per-second signals acquisition with Virtex 6 field-programmable gate array (FPGA) processing for 6U VME and VXS-based embedded computing applications. The board has 10 fast 16-bit resolution A/D converters with three Virtex-6 FPGAs, and can enable systems with as many as 180 coherent channels and 130 TeraMAC per second of processing in one chassis.The rugged Aries-V6 is compatible with legacy VME systems as well as newer ANSI/VITA 41 VXS for applications in demanding environments or in the laboratory. The Aries-V6 has 10 Analog Devices AD9467 A/D converters that provide 16-bit resolution at sample rates as fast as 250 megasamples per second with an input bandwidth of 500 MHz. The A/D converter provides an effective number of bits (ENOB) of 12.1 along with typical SFDR of 95 dBc and SNR of 74 dBFS when using a 97 MHz input.Each 6U card has one clock and trigger input for all input channels. The trigger signal may support coherent processing across several Aries-V6 boards in a system, with as many as 180 channels in one chassis. The board also has three connected Xilinx Virtex-6 FPGA sites. The two front-end FPGAs attach to the A/D converters for high-speed signal processing, while the third FPGA can support additional processing and protocol support for front-panel or backplane interfaces.

All FPGA sites on the board use FF1759 to support LXT devices that are optimized for high density logic, and SXT devices that are optimized for digital signal processing.

Each front-end FPGA on the board has two 1- and 6.4-gigabyte-per-second DDR3 memory banks for simultaneous full-rate DRFM applications and snapshot data capture for each input stream. The back end FPGA has two banks of DDR3 memory and two banks of QDR II+ memory. An onboard Gigabit Ethernet switch connects the front panel interface, backplane interfaces, FPGA nodes, and system management processor control and status monitoring. The VXS high-speed switch fabric also supports dual 10 Gigabit Ethernet using 10-gigabyte ASE-KX4 interfaces with appropriate protocol cores in the back end FPGA.

For more information contact TEK Microsystems online at www.tekmicro.com.

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