Aldec delivers low-cost, mixed language simulator to FPGA market

HENDERSON, Nev., 18 July 2009. Aldec Inc., provider of RTL simulation and electronic design automation (EDA) solutions, unveils a new low-cost mixed language RTL simulator, the Active-HDL Designer Edition. The product is designed to close a gap in the mixed RTL FPGA simulation market.

HENDERSON, Nev., 18 July 2009. Aldec Inc., provider of RTL simulation and electronic design automation (EDA) solutions, unveils a new low-cost mixed language RTL simulator, the Active-HDL Designer Edition. The product is designed to close a gap in the mixed RTL FPGA simulation market.

For FPGA designers today, a price, feature, and performance gap exists between commercial EDA simulators and FPGA vendor simulators. Active-HDL Designer Edition provides FPGA designers with a mixed language simulator for less than $2,000.

The product includes: IEEE mixed-language simulation support for VHDL, Verilog, and SystemVerilog (Design), 2X-plus performance gains over FPGA vendor-supplied RTL simulators, encrypted IP support, and no performance limitations on FPGA design size.

FPGA designers receive technical support directly from the EDA manufacturer. Software revisions and library maintenance are the same across all configurations of Active-HDL, providing a smooth upgrade path if additional functionality is required. Capabilities such as code coverage, design rule checking, DSP modeling and verification, SystemC co-simulation, transaction-level modeling, or assertion-based verification are available.

Active-HDL Designer Edition supports Windows 32/XP/Vista operating systems. The product is offered as a one-year, time-based license and available as either a node locked ($1,995) or floating ($2,495) license.

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