SANTA CLARA, Calif., 20 Feb. 2012. Intilop Inc., maker of complex ultra-low-latency networking Mega IP building blocks and systems, is introducing its 4th Gen. SX-Series 10G ultra-low-latency TCP Offload Engine (TOE) + EMAC + Altera PHY Mega IP cores running on a Stratix IV field-programmable gate array (FPGA). The TOE’s architecture is scalable, customizable, and adaptable. Intilop’s product-line solutions are available in flexible FPGA/ASIC/SoC technologies, which can accommodate a diverse set of technical design specifications.

“It was a significant achievement to port our Mega-IP block and systems solutions on a Stratix IV FPGA and deliver sub-100 nanoseconds TCP offload latency. The user-friendly features in Altera’s Quartus II software allowed us to implement logic and run it at full speed without much difficulty. The Mega IP complex takes full advantage of all the architectural features in the Stratix IV FPGA, delivering sub-100 nanosecond latency with highest performance and bandwidth,” says K. Masood, president and CTO of Intilop.

“With its TCP Offload Engine, Intilop developed a total system solution that utilizes the best of Stratix IV FPGA design features resulting in an industry-leading, low-latency Ethernet TOE solution. Beating the 100 nanosecond barrier extends the leadership position we have with our FPGA product line,” says David McIntyre, senior business manager for Altera’s computer and storage business unit.