By John McHale
NASHUA, N.H. — Engineers at Sanders, a Lockheed Martin Company in Nashua, N.H., plan to use commercial-off-the-shelf (COTS) equipment in a radiation-hardened environment for NASA`s Jet Propulsion Laboratory`s (JPL) supercomputing tech-nology program.
Under the program called Remote Exploration and Experimentation, Sanders will demonstrate a computing system capable of at least 30 million-operations-per-second per watt. In addition to making possible a new class of space science missions, Sanders officials say the technology will reduce operational costs for NASA and will contribute to the development of next-generation small satellites for deep space missions.
Sanders engineers "want to put supercomputing in space" with as much commercial-off-the-shelf equipment as possible, says Mike Harris, technical director for space electronics at Sanders.
Sanders engineers also are developing a companion radiation-hardened space processing architecture for the U.S. Air Force under the Improved Space Architecture Concept program.
Because Sanders won both contracts, NASA and Air Force officials decided they would collaborate, Harris says.
The key to integrating COTS devices in a radiation environment will be the two-level multicomputing architecture designed by Sanders, and the software implemented fault tolerance (SIFT) middleware, designed by experts at NASA JPL in Pasadena, Calif.
SIFT is a software error-detection and correction program embedded in the system, Harris says.
The development of a SIFT capability will enable COTS to operate in space without sacrificing system reliability, NASA officials claim. SIFT ensures reliability at the system rather than the component level and permits the transition of commercial technology "from shelf-to-space" in as little as 18 months, they say. The alternate to SIFT is radiation hardening individual components, which requires years to achieve and increases cost significantly.
The two-level multicomputer architecture provides an interface between application developers and system developers, Harris says. The architecture consists of a node controller, a processing element, and two network interfaces.
The node controller runs the operating system, network mapping, performance monitoring, built-in-test, and power management. The processing element takes care of application code, signal processing, libraries, and interfaces.
The system will use PowerPC 750 technology. The processors will run at 300 MHz and all together total 20 compute nodes ion the system, he adds.
The architecture uses networks such as RACEway, Myrinet, and Servernet. The Sanders architecture should lead to flight computers for missions in 2003 to 2005, Sanders officials say.