Single-chip surveillance packaged on an FPGA for homeland security introduced by team of Altera and Eutecus

SAN JOSE, Calif., 23 Oct. 2011. Altera Corp. (NASDAQ: ALTR) in San Jose, Calif., is joining hands with Eutecus Inc. in Berkeley, Calif., to introduce a 1,080-pixel, 30-frame-per-second single-chip video surveillance system packaged on one field-programmable gate array (FPGA) for surveillance and reconnaissance applications in traffic surveillance that monitors accident detection, vehicle counting, lane-exit detection, stopped traffic, red-light violations, and vehicles moving in the wrong direction.

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SAN JOSE, Calif., 23 Oct. 2011. Altera Corp. (NASDAQ: ALTR) in San Jose, Calif., is joining hands with Eutecus Inc. in Berkeley, Calif., to introduce a 1,080-pixel, 30-frame-per-second single-chip video surveillance system packaged on one field-programmable gate array (FPGA) for surveillance and reconnaissance applications in traffic surveillance that monitors accident detection, vehicle counting, lane-exit detection, stopped traffic, red-light violations, and vehicles moving in the wrong direction.

The Altera/Eutecus single-chip surveillance solution is based on the Altera Cyclone IV FPGA and the Eutecus Multi-Core Video Analytics Engine (MVE) intellectual property (IP), which performs the analytics functions in the FPGA. The surveillance system offers throughput of 60 megapixels per second with pixel precision detail not possible with traditional digital signal processing (DSP)-based approaches, Altera officials say.

The solution can be integrated into HD Internet protocol cameras, and enables the user to track dozens of user-defined rules. Users can define rules, configure alerts, and remotely update rules for events they want detected, such as a person entering a room or a restricted area in an airport terminal or a building entrance.

Altera's Cyclone IV FPGAs enable users to customize their applications with the Eutecus MVE IP that combines massively parallel algorithms and coprocessors with several Altera Nios II cores integrated into a Cyclone IV FPGA. It also comes with a software graphic user interface that enables designers to customize the event-detection parameters and rules.

For more information contact Altera online at www.altera.com, or Eutecus at paste link here.

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