BittWare introduces ATLANTiS FrameWork implemented in Altera FPGA to aid with designs at higher levels of abstraction

CONCORD, N.H., 28 June 2010. BittWare Inc. in Concord, N.H., is introducing the ATLANTiS FrameWork (AFW), an integrated system framework implemented in Altera's Stratix field-programmable gate array (FPGA) family, which provides an infrastructure that supports FPGA development at a higher abstraction level, promoting the efficient integration of existing application-specific code, as well as code reuse and portability. This allows for improved design exploration and validation, enabling designers to focus on developing their processing components rather than the infrastructure around it.

CONCORD, N.H., 28 June 2010. BittWare Inc. in Concord, N.H., is introducing the ATLANTiS FrameWork (AFW), an integrated system framework implemented in Altera's Stratix field-programmable gate array (FPGA) family, which provides an infrastructure that supports FPGA development at a higher abstraction level, promoting the efficient integration of existing application-specific code, as well as code reuse and portability. This allows for improved design exploration and validation, enabling designers to focus on developing their processing components rather than the infrastructure around it.

AFW provides reconfigurable FPGA components and the infrastructure necessary to implement, simulate, synthesize, validate, and deploy an FPGA architecture. Validated FPGA physical interfaces for all board-level I/O and communications along with proper timing constraints and I/O configurations are included.

Each component can be monitored and controlled via Altera's open standard Avalon Memory Mapped Interface. Similarly, Altera's open standard Avalon Streaming Interface is used to implement point-to-point data transport between AFW components. A set of reconfigurable fabric components expand the interconnect options for both memory mapped and streaming interfaces.

ATLANTiS FrameWork includes standard API for communication between a functional component and its sources, sinks, masters, and slaves; streaming data interconnect fabrics such as switching, mux/de-mux, FIFO, data reshaping, and common adaptors such as VIP streaming data; memory mapped fabrics such as address decoding and arbitration, interrupt handlers, reset infrastructure, and storage; validated physical interfaces with proper timing constraints and I/O configurations; SerDes Protocols providing validated SerDes components for BittWare hardware; utility functions typically used in signal processing such as scale, round, saturate, magnitude estimation, magnitude squared, and min/max; interfacing functions such as initialization, scaling, resize, reshape, and array; simulation and test resources such as scripted simulation control, standard data generators, verification and diagnostic components, and bus functional models (BFM); and example and template projects.

AFW is interconnected with BittWorks BittWare I/O (BWIO), a collection of device drivers and utilities providing AFW component drivers and a standard POSIX-based interface; portability to several different hosts including TS201, embedded FINe/NIOS and PC/LINUX; access to resources on the target board; control over AFW FPGA components; and ability to easily change code to support alternate hardware, decoupling the I/O logic from the processing logic.

For more information contact BittWare online at www.bittware.com.

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