NASHUA, N.H. – Across the defense enterprise, missions increasingly depend on networks of sensors, radios, edge computers, autonomous platforms, command elements, weapons, and space-based systems operating across large distances and multiple domains.

Chief of Space Operations Gen. Chance Saltzman described a future increasingly shaped by artificial intelligence (AI) and autonomous systems that sense, decide, and act at machine speed, and identified speed, agility, and resilience as determining advantages. [1] Achieving that vision requires more than distributing sensors and mission systems across greater distances to improve coverage, resilience, and operational reach. Those systems must remain capable of sensing, communicating, and acting as a coordinated force, even when connections are interrupted, signals change rapidly, and adversaries actively interfere. 

Defense forces are moving toward more distributed and autonomous operations in increasingly contested environments. Air Force-sponsored work on distributed operations assumes that communications may be unreliable, while Army requirements call for autonomous systems capable of operating in contested environments. [2,3] In that operating model, sensors must detect events, communications networks must move information, battle-management systems must build a common understanding, and mission systems must act.

Artificial intelligence and automation can accelerate analysis and decisions, but only after usable information reaches them. Next-generation missions require not just faster electronics, but an electronic foundation designed to support a fundamentally different way of operating. That foundation must support distributed sensing, autonomous action, processing close to the sensor or user, and coordination across communications links that change or break without warning. 

The challenge is that the response times built into today's conventional electronics were not designed to meet the combined speed, agility, and precise coordination demands now being placed on distributed autonomous systems. When a signal begins, changes, or returns after an interruption, the electronics inside a sensor or radio need time to get in step with its timing. That delay occurs before the information reaches the software, AI, or decision-maker responsible for turning it into mission action.

Related: What it will take to certify AI for commercial aviation

Fifty years of improving the same basic idea 

For more than half a century, electronics that generate frequencies, recover timing, and follow signals have relied on phase-locked loops, or PLLs. A PLL repeatedly compares a signal's timing with a reference signal and corrects the mismatch to keep them in step. Engineers have made these circuits smaller, faster, more accurate, and more efficient. Even with those advances, however, designers must balance how quickly a circuit responds, how well it rejects unwanted disturbances, and how smoothly it settles into alignment. [4-6] 

Modern all-digital phase-locked loops, or ADPLLs, use digital circuitry to measure timing differences and control the corrections. They retain the same basic feedback principle while offering advantages in power use, programmability, and integration. Within a system-on-chip, or SoC, which combines functions such as processing, control, and communications, designers can schedule tasks, calibrate circuits, and manage power to reduce the impact of predictable waiting times. 

These techniques help systems work around timing delays, but they do not remove the underlying need for the circuit to regain alignment after an unexpected signal change or interruption. 

Whether implemented with analog or digital circuitry, a conventional PLL can be tuned to react faster, but doing so can amplify certain timing disturbances or make stable operation harder to maintain. Smoother response can require more time to settle into alignment with the reference signal. Designers balance these needs through filtering, calibration, temporary data storage, and extra allowances in the design. 

These methods allow today's systems to perform extraordinarily well, but managing their response takes time, power, design effort, and added complexity. For the warfighter, the timing matters when a radio must reconnect, a brief opportunity to communicate is closing, or information from multiple sensors must arrive in time to support a decision. One area of research is whether changes to the underlying electronics can reduce some of those delays.

Changing the architecture 

Gain ICs has developed a phase-tracking architecture called the Instantaneous Loop (IL). Unlike a conventional PLL that uses feedback to correct timing differences over multiple steps, IL uses the latest signal information to produce a timing correction within the current operating cycle. Following a signal's position within its repeating cycle is known as phase tracking.

The architecture changes how the chip produces timing corrections rather than relying on a software adjustment to a conventional PLL. Gain ICs designed IL to reduce the time required to align with changing signals.

Testing the Architecture in Silicon 

Gain ICs built and tested a custom integrated circuit using 180-nanometer complementary metal-oxide-semiconductor (CMOS) manufacturing technology. The company measured how closely IL's tracking phase followed changes in a reference signal. According to Gain ICs' characterization data, the tracking phase shifted in the same direction and by the same magnitude as the reference phase at the selected measurement points. 

The reference signals used in testing were set to repeat approximately 1 million per second and then to 250 million times per second (at 1 MHz frequency and then 250 MHz frequency). At each of these frequencies, the phase transfer was measured by shifting the reference phase to opposite polarities at rates equal to one-eighth, one-fourth, and one-half of the reference frequency. At each of these samples, phase transfer was measured by taking the difference between the tracking phase and the reference phase, where zero difference corresponds to unity phase transfer. 

Gain ICs reported unity phase transfer across the selected measurement points at both reference frequencies. The tracking phase can only track to the same rate as the fastest possible shifts on the reference, switching between opposite polarities for each adjacent cycle.

Since there are two switching phases per reference cycle, the maximum rate of change of deviations on the reference phase is half the rate of change of the reference, given two phases per reference cycle: the highest possible modulation frequency on one phase of the two-phase reference signal is half the reference frequency. 

Unity phase transfer is also seen as no jitter peaking nor jitter accumulation, which would have manifested with even small-amplitude deviations on the reference phase as amplified and erratic swings of phase noise on the tracking phase, commonly seen as loss of tracking, jitter peaking, in conventional loops. 

Gain ICs reported no jitter peaking or progressive accumulation of timing error at the selected measurement points. The measurements showed unity phase transfer across the frequencies and phase-shifting rates included in the test.

Silicon testing covered frequencies through 250 MHz within the reliable measurement range of the test setup and external chip connections. Gain ICs reported no loss of signal tracking at the selected measurement points. Computer simulations project operation above 1 GHz, but that performance has not yet been demonstrated in silicon under the reported test setup.

Under the reported test conditions, the fabricated chip aligned with the incoming signal within one reference cycle and tracked the timing changes applied at the selected measurement points without measurable reduction or amplification. Gain ICs also reported no progressive buildup of timing error during those tests.

The results remain at the component level. Testing in representative radio, radar or other mission-system hardware would be needed to determine whether the measured response produces a system-level performance advantage.

References 

1. Gen. B. Chance Saltzman, Chief of Space Operations, remarks at the Air & Space Forces Association 2026 Warfare Symposium, February 23, 2026. https://www.spaceforce.mil/News/Article-Display/Article/4412751/remarks-by-cso-gen-chance-saltzman-at-the-air-and-space-forces-association-2026/ 

2. M. Priebe, A. J. Vick, J. L. Heim, and M. L. Smith, Distributed Operations in a Contested Environment: Implications for USAF Force Presentation, RAND Project AIR FORCE, RR-2959-AF, 2019. https://www.rand.org/pubs/research_reports/RR2959.html 

3. U.S. Army Program Manager Uncrewed Aircraft Systems, "Launched Effects," capability notice, August 5, 2025. https://sam.gov/opp/9a056b2390d240a59dc9cd7a42ad1810/view 

4. F. M. Gardner, Phaselock Techniques. New York: Wiley, 1966. 

5. T. Watanabe and S. Yamauchi, "An All-Digital PLL for Frequency Multiplication by 4 to 1022 With Seven-Cycle Lock Time," IEEE Journal of Solid-State Circuits, vol. 38, no. 2, pp. 198-204, February 2003. 

6. M. J. E. Lee et al., "Jitter Transfer Characteristics of Delay-Locked Loops - Theories and Design Techniques," IEEE Journal of Solid-State Circuits, vol. 38, no. 4, pp. 614-621, April 2003.