MEN Micro Inc. in Ambler, Pa., is offering its FPGA-based Universal Submodule as XMC and PMC mezzanine cards. The P699 XMC and P598 conduction-cooled PMC modules use one or more IP cores in a field-programmable gate array (FPGA). The use of Cyclone FPGAs on the two cards enables I/O combinations in a small space. The P699 XMC uses a Cyclone III FPGA with 24,624 LE (logic elements) and the P598 conduction-cooled PMC features a Cyclone II with 33,216 LE. Different IP cores enable users to change the functionality of either card without modifying the main module. The line drivers are implemented on the individually designed USM submodule that plugs into the main XMC or conduction-cooled PMC. The IP cores operate in temperatures from -40 to 85 degrees Celsius. A Nios soft-core processor, which features 32 megabytes of DDR2 SDRAM main memory and 2 megabytes (P598) or 4 megabytes (P699) Flash memory, is implemented on the FPGA providing local intelligence to the main module. A USM development package includes a main PMC with a USM submodule, test hardware, and an FPGA package with a Nios CPU, memory control, connection to the PMC, Avalon/Wishbone bridges, and detailed documentation. The Wishbone Bus Maker tool from MEN is included for development of IP cores on the standard Wishbone bus. The Nios core and the development of IP cores on the Avalon bus require Altera’s Quartus II design environment, including the SOPC builder. For more information, visit MEN Micro online at www.menmicro.com.