By John Rhea
CHELMSFORD, Mass. - Engineers at Mercury Computer Systems in Chelmsford, Mass., were to unveil an enhancement to their multicomputer system architecture, designated RACE++, this month at the Embedded Systems Conference in San Francisco.
In addition, company officials already met with representatives of the 45 or so third-party users late last month to map out a strategy for product announcements early next year.
Barry Isenstein, vice president for advanced technology, says the new architecture is scaleable across the board for image processing in military and medical diagnostic applications. "Our audience is performance hungry," he says, adding that product shipments based on RACE++ will start in mid-1999.
The net accomplishment of the architecture is to more than double aggregate bandwidth - from 480 megabytes per second to a gigabyte per second.
Designers will do this by using a new eight-port crossbar built out of an applications specific integrated circuit designed at Mercury that provides greater connectivity than the six-port crossbar in the current RACE architecture.
Data rates are also increased slightly from 40 to 66 MHz. Consequently, designers can quadruple the number of processors to be supported from 1,000 to 4,000. The new architecture is also backward compatible with some 60 products made at the third parties to the current RACE architecture.
The evolving architecture, in conjunction with anticipated improvements in functional density at the chip level, should continue to push up performance density of computational systems, Isenstein says.
He recalls that an advanced system known as Project Platinum achieved a density of 10 gigaflops per cubic feet in 1994, but this required what he describes as "heroic packaging," including extensive use of multichip modules.
Mercury`s current top-of-the-line system, used at MIT Lincoln Labs for space-time adaptive processing, delivers 120 gigaflops in 120 cubic feet, or 12 gigaflops per cubic feet - and without heroic packaging. Isenstein says he figures that kind of packaging, including liquid cooling, could probably push density up by at least another factor of four.
The long-term goal, Isenstein says, is to increase functional density to 100 gigaflops per cubic foot in the near term and then on to a teraflop (trillion floating-point operations) early in the new century.
System architecture is part of the equation, providing the increased connectivity, but packaging, cooling, and chip improvements will also figure in this effort.