Congratulations to Sanders on clockless logic project

In the February 1998 issue of Military & Aerospace Electronics, a story headlined "Sanders uses clockless logic to improve the efficiency of signal" mentioned the advantages of the "clockless logic." The quoted Null Convention Logic (NCL) was not explained but the original computer of the Computer Project directed by John Von Neumann at the Institute for Advanced Study (IAS) in Princeton, N.J., was specifically designed using aynchronous logic, at least in the arithmetic unit. The machine has be

Apr 1st, 1998

To The Editor:

In the February 1998 issue of Military & Aerospace Electronics, a story headlined "Sanders uses clockless logic to improve the efficiency of signal" mentioned the advantages of the "clockless logic." The quoted Null Convention Logic (NCL) was not explained but the original computer of the Computer Project directed by John Von Neumann at the Institute for Advanced Study (IAS) in Princeton, N.J., was specifically designed using aynchronous logic, at least in the arithmetic unit. The machine has been in the Smithsonian American History Museum for decades.

I have also designed a machine, named SOLO, for the U.S. National Security Agency starting in 1955 using similar logic. In the 1970s, I also designed a 16-bit CMOS processor on a sapphire substrate using mostly asynchronous logic. The process was single metal non-self aligned gate with 0.5-mil metal to cover a 0.3-mil channel length. In today`s term, the channel was 7.5 microns! I had no choice but use the simple IAS machine architecture because of the monstrous feature size and the need to fit the only commercial leadless carrier by 3M with 48 pads.

The transistors were very weak and I had to adopt a fan-out limit of three (mostly) so that features such as parallel carry were impractical. There was no space either. Even with 10 volts of supply, I was only able to achieve one-half of my design goals of 1 MIPS. However, I was really surprised that my technician pointed to the Simpson meter that registered 2.5 ma or 25 mw. I can support Sanders` claim of low transistor count because that chip took only about 4,400 transistors. The article did not mention the testing mode Sanders used. I did have two one-shots, one of them can be indefinitely extended for testing with a voltmeter or speeded up during internal cycles of multiplication, where carry propagation was disabled.

Sanders should be congratulated for rediscovering the advantages of asynchronous logic which some mistakenly construed as harder to design. Sanders did have an advantage over my project in the 1970s because I did not have any EDA support except for a tiny Applicon machine that converted hand digitized manual layouts into mask generation tape.

I was fortunate that I had a couple of very bright young engineers one each for layout and testing plus a most unusual technician that helped to build special testers. A one-person shop made all the prototype wafers that the semi-conductor division of the company I worked for cannot. It took us much longer than what could be a 6-month job with today`s tools. Today`s process and feature sizes may even make that processor chip too small to handle.

SY Wong

retired computer scientist

Los Angeles

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