By John Rhea
SANTA CLARA, Calif. - A new team formed to supply application-specific integrated circuits (ASICs) to military and aerospace systems designers has begun selling devices - CMOS gate arrays and standard cells of as many as 700,000 raw gates, with 0.65-micron geometries.
Current planning calls for team members to supply ASICs in geometries of 0.35 micron later this year, and 0.25 micron in 1998.
Heading the team, known as the Customization Business Unit (CBU), is National Semiconductor Corp. of Santa Clara, Calif. Teaming with National are two design firms, Cadence Design Systems in San Jose, Calif., which specializes in design services and automation tools, and Aspec Technology of Sunnyvale, Calif., a gate array architecture firm. Product line director is Joe Shah in National`s Mil/Aero Division.
The CBU members will focus on avionics, electronic warfare, radar, signal processing, and telecommunications designs, initially providing custom and semi-custom products and eventually "systems on a chip" based on National`s core competency in analog and mixed-signal technologies.
Company officials would not identify any of the initial customers other than to note that they were defense and aerospace prime contractors.
The rationale behind the one-stop shopping center is the decline of integrated circuit vendors serving this market - down from 18 to six in recent years. The team approaches acknowledge the difficulty that any single company would have providing a full range of ASIC design, implementation, and manufacturing services.
The team`s goal is to deliver first-time working silicon in 12 weeks, says Brad Paulsen, director of Mil/Aero marketing at National. Packing is either ceramic or plastic of as many as 50 pins, including ball grid array packages.
