By John Keller
NASHUA, N.H. - Defense researchers are attempting to make a revolutionary technological breakthrough in embedded computing by developing configurable logic that is able to execute math, functions, and algorithms in hardware, rather than as software instructions.
This project, called Context Switching Reconfigurable Computing (CSRC) may hold the potential to render an entire generation of digital signal processors (DSPs), software, and perhaps even microprocessors obsolete.
The CSRC project seeks to develop computers where "the logic itself becomes the function you want to process, rather than a computer program sitting off in a memory; it involves no program, and no software," says Mike Harris, director of the digital processing technology center at Sanders, a Lockheed Martin Company, in Nashua, N.H.
"Context switching reconfigurability is flying through enemy air defenses, where I have been using my computing assets as electronic warfare assets. Now I`m flying over a target zone and want the computer to do image processing for automatic target recognition," Harris says. "Like using software, I would be running a different program."
Scientists from Sanders, Xilinx Inc. of San Jose, Calif., and the University of California at Los Angeles are working on CSRC under supervision of the U.S. Defense Advanced Research Projects Agency (DARPA). Administering the $6.9 million DARPA contract is the U.S. Air Force Rome Laboratory in Rome, N.Y.
This capability has the potential to reduce the size and weight of electronic systems, as well as improve reliability, by merging what today are separate subsystems into a single system, Harris says. "You could use the same hardware for electronic warfare, communications, image processing, and many other applications."
Key to the project is creating computing devices that are able to change in the blink of an eye. "This is the task of scientists at Xilinx, who have made their reputations designing adaptable hardware such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs).
"Our primary challenge is trying to make some fairly significant breakthroughs by eliminating or reducing to an insignificant fraction the overhead associated with switching a device from a program that is running, to a new program," explains Dave Lautzenheiser, co-principle investigator on the CSRC program at Xilinx.
"A lot of the underlying architecture and technology that has been developed at Xilinx addresses a fairly large portion of the requirements of these applications, but it doesn`t address it in an environment where you want to switch between different contexts," Lautzenheiser says.
"The process by which you program the currently available FPGA products is fairly slow - hundreds of milliseconds," Lautzenheiser says. "We are asking, how can we make the context switching time effectively zero? The goal is to make context switching time such a small fraction of overall time spent performing some process that it basically disappears."
Xilinx is expected to deliver hardware capable of extremely fast context switching by late 1999, Harris says.
Sanders experts, meanwhile, will perform tradeoff studies, map algorithms, develop system programming tools, and design prototype modules.
"We can achieve somewhere around a 20-1 to a 100-1 improvement in size, weight, and power," Harris says. "It enables innovative systems designs so you can put mission planning and automatic target recognition aboard in addition to other avionics systems. You can`t afford the weight to do all that in one little airplane."
The performance of adaptive computers also is expected to increase dramatically over conventional microprocessor-, DSP-, and software-based systems. The proof of that came in a Sanders project three years ago called CHAMP, short for Configurable Hardware Algorithm Mappable Pre-processor, Harris says.
Air Force experts handed engineers at Sanders and at Texas Instruments an infrared search and track algorithm to execute - Sanders on the CHAMP, and Texas Instruments on one of the company`s DSPs, Harris says. "CHAMP ran at 305 frames per second, and the TI device was 12 frames per second," he says. "This is a 30-1 reduction in the number of boards necessary, and an order of magnitude improvement in latency."
The Configurable Hardware Algorithm Mappable Pre-processor from Sanders demonstrated that adaptive hardware can outperform conventional microprocessor-and-software systems