The future role of chip-scale packaging in COTS reliability

May 1, 2001
The relentless trend toward ever-shrinking components for electronic systems designs is driving development of new packaging technologies such as chip scale packages, better known as CSPs.

By Keith Gurnett and Tom Adams

The relentless trend toward ever-shrinking components for electronic systems designs is driving development of new packaging technologies such as chip scale packages, better known as CSPs.

These CSPs are especially attractive for use in commercial off-the-shelf (COTS) sourcing in military and high-reliability applications because these packages feature fine traces, extremely small pitches, high reliability, long life cycles, and — perhaps most significantly — affordability in manufacturing.

The primary reason that systems designers use the CSP in commercial applications is its small size and high operating speed in assembled integrated circuits (ICs).

The recent development of on-chip speed-enhancing technologies such as 0.18-micron features, copper interconnect, and low-k dielectrics press the need to reduce parasitic speed-reducing factors of the traces in the package.

At the same time, the need to reduce manufacturing costs is driving chip makers to test and package right on the wafer before singulation into individual devices. Some CSPs already incorporate wafer scale packaging, and promise previously unattainable economies of scale along with small size and high speed. Fortunately, wafer scale packaging that integrates back end of line (BEOL) into the clean fab environment, along with the fabs manufacturing disciplines, may increase reliability.


During the dual inline package (DIP) era in the 1960s and 1970s, size was not a major driving force because pin counts were low. The introduction of processors, memory chips, and complex ICs soon increased package size. But the increasing length of the lead-out trace raised the trace parasitic impedance and decreased off chip speed performance. Reducing lead pitch from the DIP's 0.1 inch to the 0.05 inch pitch of four-sided quad packs increased off chip speed to acceptable levels.

Ceramic chip carriers, plastic leadless chip carriers (PLCCs), plastic quad flat packages (PQFPs), and small outline integrated circuits (SOICs) also tried to eliminate parasitic impedance by shortening leads and using finer pitches. None of these packages, though, has achieved the major penetration of 96 percent into IC packaging that the DIP attained in the 1980s.

Steadily rising pin counts created problems across the whole catalogue of IC package types. For manufacturing, these problems included molding and lead-frame tooling, assembly layout simplification, automated handling through test and assembly, and IC type compatibility among the different suppliers caused difficulties. Chip designers could meet but few of these parameters with any one type of package without increasing either costs or assembly problems. While all of the new package types reduced size and increased performance speed, the most successful one was the quad SOIC.

The hermeticity of ceramic or metal packaging dominated in the early days of IC packages because chip passivation was so poor that designers needed ceramic or metal packages to prevent leakage into the package. Great improvements in passivation changed this picture, and today fewer than 3 percent of all IC packages are hermetic.

The major improvements in die surface passivation left metallization and surface contamination as the major environmental and reliability hazards for the chip. Improving surface passivation and new metallization systems reduced these hazards. Today the package's main function is to protect sensitive electronics from these remaining failure mechanisms, and these factors should be considered in Direct Chip Attach (DCA) designs requiring open chip work.

The three major types of DCA technology — chip-on-board (COB), multi-chip modules (MCM), and flip chip (FC) — have grown slowly because of the hidden commercial problem of the chip specification interface. This interface applies to electrical and mechanical interconnection aspects of the IC and its performance.

Chip shrinks and dual sourcing create problems with pad interface patterns. Testability at full power and speed creates dubious electrical performance criteria when testing at bare chip level. Known Good Die (KGD), the one potential remedy, succeeded only in niche products where size and speed are at a premium. CSPs should effectively take over the role of the DCA due to their improved testability and ability to meet safe handling criteria.

Today's product

Today, the electronic packaging industry invests intensively in Ball Connect Technique (BCT) to create a myriad of package offerings, each purporting to provide some unique solution to the end product. Flip chips, BGAs, and several types of CSPs employ BCT. With these advances, BCT is poised to meet a wide range of package market requirements.

One important consideration is the difference in scale sizes between chips and boards. Semiconductor features are measured in microns. The typical line and space on a mature semiconductor is one micron. On a leading-edge semiconductor, features can be as small as 0.18 micron.

In the printed wiring board (PWB) world, features are measured in mils (25 microns). Typical line and space is 5 mil; leading edge is 3 mil. With this large disparity in features size that in DCA assembly designers must make some adaptation. One possibility is adding silicon to ICs to make compatible interconnect sizes. Alternatively, some type of interposer or system PWB might make the line and space features compatible.

Current product requirements and major improvements in semiconductor technology are driving a huge increase in the need for pin counts of 1,000 and more; some CSPs, in fact, reportedly have pin counts as high as 2,500.

A logic array design with more than 1,000 bond pads is almost always pad limited in terms of periphery bonding; that is, bond pads are so numerous that they must be distributed across the face of the chip. Even with the most aggressive of today's wire bond pitches (50 micron effective staggered) the 1,000 pad die would be at least 1.5 centimeters square. By comparison, using a high-density substrate technology combined with BCT and area bonding, the die size could be reduced to 1.0 centimeters square. In this case, the die cost reduction afforded by the use of BCT area bonding is the primary driving force for its use. This, along with the disparity in feature size previously mentioned leverages the need for area bonding as against periphery bonding.

Once chip size rises above 1 centimeter square the defect density curve rises dramatically. By creating flatter surfaces for lithography, chemical mechanical polishing (CMP) has raised this critical size to 1.5 centimeters with reasonable yields. This size limitation is one of the reasons why lower feature sizes and chip shrinks are necessary. Now yield conservation techniques include area bonding.

With the transition to 300-millimeter wafers combine with geometries of 0.13 microns there are hundreds of millions of vias and contacts and up to seven levels of metal in some of the devices currently in production. Intel's transition from the P3 to P4 processor raised the active device count per chip from 10 million to 42 million with six levels of interconnection.

Finding the one or two yield-killing defects is difficult and cannot be done in an integrated fashion because tools required for detection are too expensive and only becomes viable in high volume product. The down side to this is finding too many partial defects that neither damage yield nor cause reliability problems.

One major change in the industry recently has been the rapidly growing importance placed on packaging. Instead of simply protecting the die, the package is also playing a large role in ensuring signal integrity. At the same time that packaging technologies are advancing, co-design of chip and package is becoming the necessity. Multi-chip and 3D packaging are increasingly popular methods for saving space as well as viable alternatives to system-on-a-chip integration.

Yield and infant mortality

Over many years the IC industry has manufactured products that conform to the classic "bathtub" life curve for mature products and processes. Early infant mortality failures and failures near the end of the expected life are the most frequent; between these two extremes, the failure rate is low. For CSPs as for other package types, infant mortality failures require extensive testing and the production of many batches with corrected tooling before an accurate assessment can be made and the appropriate burn-in conditions can be stipulated.

Current state-of-the-art fabs process 200-millimeter wafers at rates of 5,000 or more per week. The move to 300-millimeter wafers will substantially increase die/wafer output and create huge amounts of reliability and life data. Yield management needs to improve substantially for effective use of the large database. Currently, the output success rate after back end processing is only 95 percent on a typical high volume line with a mature process.

Product viability, time to market, and competition mean that more failures are contained in the early life of an IC product. For immature devices the front end of the bathtub curve is important and a significant indicator of quality and infant mortality. The wear out tail is not evident, as wear out mechanisms have not yet been identified.

Immature products such as CSPs can have a final packaged test yield of 80 percent or less until the point is reached when process feedback and corrections are effectively in place. This early part of the life cycle can be a killer for DCA packaging, especially in sub-systems containing many chip functions. Unfortunately, today's commercial market place with its short life cycle and the importance of 'time to market' only increases the infant mortality risk.

The level of infant mortality depends mainly on maturity of process, complexity of circuit, number of fab processes, die size, and circuit density.

More specialized ICs demand a different balance between infant mortality and process/tooling adjustment because of the lower device demand. A burn-in process by the chip source or original equipment manufacturer (OEM) eradicates the early life failures with this type of product, giving a reasonable assembly yield and product field performance. Unique, low-volume product and mass production "jellybean" products do not mix within one fab line.

Most electronic systems use both types of product and must accept a wide and variable non-burn-in yield across the device types within a subsystem. Burn-in, pre-testing, and the supplier history help the system assembler negotiate these yield problems in the assembly phase. Full environmental, high frequency, power testing and burn-in on open chips can be difficult. Failures cannot be definitely attributed to the chip supplier or the OEM, compromising the commercial interface.

Comparing assembly phase yield for various chip yields against chip count shows that the effect of marginal processing failures stressed to failure by the assembly processes is considerable. In DCA designs, back end process failures further reduce module yield in a similar way. The further effect of early infant mortality has a similar cumulative mortality rate increase with chip count. This is the fundamental reason why chip suppliers need a successful chip scale package.

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