Officials of the U.S. Defense Advanced Research Projects Agency (DARPA) in Arlington, Va., announced an $11.8 million sole-source contract Tuesday to the USC Information Sciences Institute in Los Angeles for the Circuit Realization at Faster Timescales (CRAFT) – FinFET Foundry/Design Aggregation Services military chips program.
DARPA officials are asking USC scientists to develop a custom IC design flow to reduce the effort to design high-performance custom ICs; help port IC designs to secondary foundries and more advanced technologies; and reuse of IC intellectual property.
To maintain technology dominance, the U.S. military is developing next-generation systems that require high computational performance in a power-constrained environment. The problem, however, is these technologies cannot be manufactured fast enough. Systems designers today must choose between high performance and low power consumption.
For the most crucial applications, systems designers must choose between a high performing, custom ICs that requires years to design and fabricate, or settle for a 100-times lower-performing general-purpose processor that can be programmed in months.
The DARPA CRAFT program seeks to demonstrate a custom IC design flow and methodology in a leading-edge commercial 16- or 14-nanometer fab, port these designs to new foundry process flows, and increase design reuse by providing a repository for secure storage and distribution of design elements.
The CRAFT has three technical goals: reducing custom IC design and fab cycle time by 10X with new software tools; enabling a 50 percent reuse of critical military IC modules with an intellectual property (IP) repository system; and enabling flexible chip fabrication by porting a technology node from one foundry to another, or migrating from one design node to another design node at the same foundry.
To meet these goals, DARPA needs to build custom ICs using the FinFET leading-edge CMOS process node because of this technology's density, performance, and power advantages. To access this technology, the CRAFT program needs FinFET foundry access, and this is where USC Information Sciences Institute comes in.
USC will provide a design aggregation service for CRAFT contractors as they perform dedicated and foundry-driven FinFET multi-project wafer (MPW) shuttle runs. USC Information Sciences has prior experience in working with leading-edge technologies, and will act as the primary interface between the foundries and DARPA.
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USC also will collect individual designs, produce an aggregation of these designs to create the floorplan for the full mask set, and will insert MOSIS designed test structures to provide vital early assessment of the designs, DARPA officials say.
USC will train military and university designers how to use the technology, and maintain and distribute foundry tools and models. USC can provide these services because it can work with classified data and has experience in helping design teams develop and integrate technologies at the FinFET technology node that CRAFT will use, DARPA officials say.
USC also has an automated infrastructure that provides automated and fast release of process design kits to shuttle run users, DARPA officials say. The contract includes options for phases 2 and 3 that are not yet exercised.
On this contract USC will do the work in Marina Del Rey, Calif., and should be finished by the end of phase 1 in February 2016. For more information contact the USC Information Sciences Institute online at www.isi.edu, or DARPA at www.darpa.mil.
