FMC site support based on the VITA 57 mezzanine standard for FPGA I/O provides SerDes and LVDS, along with clocks, I2C, and JTAG connected directly to the Stratix V enabling designers to customize the S5PE-F with a variety of I/O or processor FMCs.
A new memory structure provides flexibility with two SODIMM sites that support as much as 16 gigabits of DDR3 SDRAM with optional error-correcting codes (ECC) as well as options for as much as 1 gigabytes of RLDRAM3 and as much as 72 megabytes of QDRII+.
The options for FMC I/O and memory SODIMMs combined with BittWare’s FPGA IP Libraries enhances productivity and portability and allows even greater processing efficiency.
Features include VITA 57 FMC site for I/O with full high pin count support; Altera Stratix V GX/GS; Configuration via Protocol (CvP) supported; PCI Express x8 interface supporting Gen1, Gen2, or Gen3; Four SATA connectors with speeds of 6 gigabits per second each; timestamping support; utility I/O includes USB 2.0, RS-232, and JTAG; memory options of as much as 16 gigabits of DDR3 SDRAM with ECC; as much as 1 gigabyte RLDRAM3; and as much as 72 megabytes of QDRII+.
For more information contact BittWare online at www.bittware.com.
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