Radiation-tolerant 3U CompactPCI single-board computer introduced by Aitech for space applications

CHATSWORTH, Calif., 14 Aug. 2012. Aitech Defense Systems Inc. in Chatsworth, Calif., is introducing the SP0 space-qualified, radiation-tolerant 3U CompactPCI single-board computer for orbiting satellites, manned spacecraft, and other space applications.

Aug 14th, 2012
Radiation-tolerant 3U CompactPCI single-board computer introduced by Aitech for space applications
Radiation-tolerant 3U CompactPCI single-board computer introduced by Aitech for space applications

CHATSWORTH, Calif., 14 Aug. 2012. Aitech Defense Systems Inc. in Chatsworth, Calif., is introducing the SP0 space-qualified, radiation-tolerant 3U CompactPCI single-board computer for orbiting satellites, manned spacecraft, and other space applications.

The MPC8548E PowerQUICC-III PowerPC-based embedded computing board consumes 10 Watts of power and achieves a processing speed of 1.17 GHz and 333.3 MHz of core complex bus (CCB) and DDR-1 memory speeds.

The SP0's processor includes an e500 system-on-chip (SoC) that blends an L1 cache with 32 kilobits instruction, 32 kilobits data, and a 512-kilobit L2 cache. A 1-gigabyte user Flash of is standard, with the option to expand to as much as eight gigabytes.

An on-board memory also includes as much as 512 megabytes of fast DDR1 SDRAM with ECC protection for high data integrity as well as 512 kilobits of redundant boot Flash.

I/O routes to the rear-panel connectors, and includes two Gigabit Ethernet ports, four asynchronous, high-speed serial communications ports and as many as five general purpose discrete I/O channels.

An included industry-standard PMC slot, either air- or conduction-cooled, accommodates additional modules and on-board functionality. The board also has as many as eight PCI Express lanes or four Serial RapidIO lanes, and dual PCI buses.

When operating as a system controller, instead of as a peripheral card, the SP0 supports as many as seven additional cards on the PCI backplane with clock signals and interrupt and arbitration support.

Three watchdog timers are included. One watch dog timer, located within the SoC processor, generates an internal CPU interrupt to alert the application of a pending fault. After the first timer expires and then the second timer expires, a non-maskable hardware reset also resets the entire board.

Located in the on-board FPGA, the third timer can reset the whole board or only certain I/O devices after the expiration period.

A 1 pulse per second (PPS) timer provides a system backplane and external heartbeat for synchronization to other autonomous computing and communications subsystems on the satellite bus or spacecraft platform.

For more information contact Aitech online at www.rugged.com

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