DARPA asks industry for affordable, low-volume integrated circuit manufacturing

ARLINGTON, Va., 20 Dec. 2009. Scientists at the U.S. Defense Advanced Research Projects Agency (DARPA) in Arlington, Va., are asking industry to come up with news ways of designing integrated circuits for affordable, low-volume nanofabrication for U.S. Department of Defense (DOD) applications.

Dec 20th, 2009

Posted by John Keller

ARLINGTON, Va., 20 Dec. 2009. Scientists at the U.S. Defense Advanced Research Projects Agency (DARPA) in Arlington, Va., are asking industry to come up with news ways of designing integrated circuits for affordable, low-volume nanofabrication for U.S. Department of Defense (DOD) applications.

DARPA issued a broad agency announcement Friday (DARPA-BAA-10-12) for the Gratings of Regular Arrays and Trim Exposures (GRATE) program to develop revolutionary circuit design approaches and grating-based lithography tools.

Scientists from the DARPA Microsystems Technology Office (MTO) expect these approaches to simplify circuit layout by using extremely regular geometries by using ultra-high-resolution grating patterns, which can be fabricated at high throughput using either mask-based or maskless (interference) lithography.

DARPA experts are looking for a integrated circuit microfabrication approach that reduces the costs of designing custom application-specific integrated circuits (ASICs) by enabling maskless interference-based patterning, and improving fabrication yields.

The integrated circuit industry today is developing the fabrication technology necessary to manufacture 32-nanometer CMOS devices and smaller, DARPA officials say. The problem, however, is that chip fabs generally are geared for high-volume manufacturing.

Instead, DARPA scientists are looking for ways to make custom electronics at much lower volumes, where current commercial microelectronic manufacturing methods are not cost-effective in this regime, DARPA officials say.

The GRATE program, on the other hand, focuses on patterning requirements beyond the current industry state-of-the-art that emphasize affordable solutions for low-volume DOD applications.

One part of the GRATE program focuses on digital logic and memory, and the other part of the program focuses on analog/RF and mixed-signal designs to scale current RF technology patterning two nodes beyond the current state of the art using existing tools and masks.

DARPA officials have $15 million for this project, and say they expect to award one or two contracts. For those interested, full proposals are due to DARPA by 3 Feb. 2010.

For questions, contact Michael Fritze, the DARPA/MTO program manager, by e-mail at DARPA-BAA-10-12@darpa.mil or by fax at 703-696-2206.

More information on this contracting opportunity is online at https://www.fbo.gov/index?s=opportunity&mode=form&id=7d2c066dd975573de03d15b5b853d1c0&tab=core&_cview=0.

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