Stratix III FPGAs feature hardware architecture advancements and Quartus II software enhancements, translating to 50 percent lower power, 25 percent higher performance, and 2 times the density compared to previous generation Stratix II devices.
Reduced power consumption is achieved by utilizing Altera's Programmable Power Technology, which enables every programmable logic array block (LAB), DSP block, and memory block to operate independently in high-speed or low-power mode.
The PowerPlay feature in Quartus II software version 6.1 automatically analyzes the design and identifies which blocks are in the critical path and demand the highest performance, setting these to high-speed mode. All other logic is automatically put into low-power mode. The second power-optimizing feature, Selectable Core Voltage, provides the designer options to select either 1.1V for designs needing the highest performance or 0.9V for designs requiring minimum power consumption.
In addition to the Quartus II design software, tools from leading EDA vendors Aldec Inc. (System Verification Environment), Magma Design Automation Inc. (Blast FPGA), Mentor Graphics Corporation (Precision Synthesis), and Synplicity Inc. (Synplify Pro FPGA synthesis and Synplify DSP software) support the Stratix III device family.
Engineering samples of the first member of the Stratix III device family will be available in the third quarter of 2007. Customers can start their Stratix III designs today using Altera's Quartus II design software version 6.1. 1000-unit pricing starts at $549 for the EP3SL150 device in 2007.