High-definition IP surveillance camera packaged on one FPGA introduced by Altera

SAN JOSE, Calif., 28 June 2010. Altera Corp. in San Jose, Calif., is introducing a high-definition (HD), surveillance internet protocol (IP) camera reference design on one field-programmable gate array (FPGA). This camera-on-FPGA has the Altera Cyclone III or Cyclone IV FPGA and intellectual property from Eyelytics and Apical supporting the AltaSens 1080p60 A3372E3-4T and Aptina 720p60 MT9M033 HD wide dynamic range (WDR) CMOS image sensors.

SAN JOSE, Calif., 28 June 2010. Altera Corp. in San Jose, Calif., is introducing a high-definition (HD) internet protocol (IP) surveillance camera reference design on one field-programmable gate array (FPGA).

This camera-on-FPGA has the Altera Cyclone III or Cyclone IV FPGA integrated circuits and intellectual property from Eyelytics and Apical supporting the AltaSens 1080p60 A3372E3-4T and Aptina 720p60 MT9M033 HD wide dynamic range (WDR) CMOS image sensors.

The offers surveillance equipment manufacturers the ability to reduce space on board products, lower power consumption, increase flexibility and reduce development time compared to previous architectures using traditional digital signal processors (DSPs) and application-specific standard products (ASSPs).

Altera's Cyclone series FPGAs deliver the bandwidth and processing performance needed, handling large amounts of data generated by today's HD WDR CMOS image sensors. In previous designs, HD WDR camera systems required FPGAs to perform the front end data processing while a DSP or an ASSP handled the back end video encoding. Now, all of these chips can be replaced by one Altera FPGA.

Features include Apical's ISP WDR processing iridix together with advanced temporal and spatial noise reduction; Apical's checkerboard demosaic core for the Altasens A3372E3-4T WDR mode; 3A functions, such as auto exposure and auto white balance implemented in software on Altera's Nios II embedded soft core processor; Eyelytics H.264 video encoder, capable of 720-line progressive 30 frames-per-second encoding or 1080-line progressive 15 frames-per-second encoding in main profile; and Altera's triple-speed Ethernet MAC intellectual property core.

All camera designers have to do is customize the FPGA with their own software for motion detection, and pan, tilt and zoom control.

By eliminating the need for DSPs or ASSPs and combining all of these functions into one Altera FPGA, designers can take advantage of the cost and power savings with reduced board space. Altera's single-chip solution reduces power consumption by more than 50 percent compared to previous designs.

For more information contact Altera online at www.altera.com.

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