Sensing to action in microseconds: modern day defensive edge processing

PITTSBURGH - A targeting system that takes 80 milliseconds to close its processing loop isn’t slow — it’s broken. At the velocities and threat tempos of modern combat, 80ms is the difference between a successful intercept and a miss. Yet that figure represents the realistic latency of a traditional defense electronics pipeline: image sensor to frame grabber to CPU, or antenna to discrete ADC to FPGA to processor. Each handoff adds delay. Each additional board adds weight, volume, and a failure point.

Defense systems have always demanded low latency. What’s changed is the platform. Drones, autonomous weapon systems, and vehicle-mounted sensors cannot carry rack-mounted computing infrastructure. They need the full sensing-to-decision pipeline compressed into something that fits inside a lunchbox and runs on tens of watts — not hundreds.

Traditional architectures don’t scale down gracefully. An imaging chain — discrete image sensor, frame grabber, industrial vision controller, CPU, GPU — sprawls across boards and consumes power that SWaP-C-constrained platforms don’t have. RF signal processing stacks are worse: antenna, RF front end, separate ADC and DAC chips, FPGA, processor, and the boards to mount all of it. Networking at the edge compounds the problem further: Embedded systems that once ran at 1 Gb/s are now pushing 10G, 25G, and 100G, with tight synchronization demands addressed by IEEE 1588, Time-Sensitive Networking (TSN), and high-availability redundancy protocols like HSR/PRP. The latency toll for all of this? Tens to hundreds of milliseconds. In targeting, electronic warfare, and ISR, that’s not a performance gap — it’s mission risk.

Three technology developments are collapsing this pipeline. Advanced SoC FPGAs now integrate programmable logic, DSP blocks, AI engines, and ARM CPU cores on a single device. High-speed cameras with in-sensor FPGA processing move the intelligence to the point of capture, before data ever leaves the sensor. RF Systems on Chip (RFSoC) eliminate the discrete ADC layer entirely, enabling direct RF sampling and real-time signal processing in hardware. None of these are emerging technologies waiting on production readiness. They’re available now, in deployable form factors, and increasingly within reach of defense programs that previously couldn’t justify the engineering investment.

FPGAs evolve: programmable logic to SoC

Earlier FPGAs were powerful but architecturally isolated. They handled parallel processing tasks exceptionally well but still required external CPUs for control logic and discrete ADCs for analog signal acquisition. The integration story was fragmented: multiple chips, multiple boards, multiple failure modes.

Today’s SoC FPGAs consolidate what used to be an entire board stack onto a single device. AMD’s Versal AI Core series, for example, integrates FPGA programmable logic, hardened DSP engines, AI inference engines, and quad-core ARM Cortex processors in one package. The external CPU is gone. The discrete signal processing chain is gone. What remains is a single, programmable substrate that the designer allocates by function.

The latency numbers quantify what this means operationally. Traditional CPU-centric pipelines — even well-optimized ones — deliver processing latency in the range of 10 to 100 milliseconds. FPGA-based architectures, processing data in parallel hardware rather than sequential software, bring that figure to 4–20 microseconds. That’s a 50x to 250x improvement. For a closed-loop control system — a gimbal tracking a fast-moving target, a guidance system correcting course mid-flight — the difference between 100ms and sub-millisecond response time is binary: either the system can close the loop, or it can’t.

The SWaP-C case is equally compelling. Modern FPGA System-on-Module (SoM) boards now achieve form factors as small as 4x5 cm. Thermal profiles are manageable without heavy cooling infrastructure.

 Performance-per-watt at this scale has no credible competition from GPU-based alternatives in edge-deployed, environmentally hardened applications.

AMD Embedded+ represents the current leading edge of this consolidation. It places a Ryzen x86 processor alongside a Versal AI SoC — FPGA fabric, AI inference engines, and ARM Cortex cores — on a single Mini-ITX board drawing under 50W. It supports up to 8 GMSL cameras, standard frame grabber protocols, and high-speed Ethernet vision interfaces. A defense OEM can distribute workloads across x86 software, FPGA parallel logic, and AI inference engines on one board, assigning each task to whichever compute resource handles it best.

One frequently overlooked development is accessibility. AMD’s Vitis HLS toolchain allows C and C++ algorithms to compile directly into FPGA hardware logic — defense software engineers who know C can now target FPGA fabric directly, without dedicated VHDL or Verilog expertise.

High-speed imaging continues to expand

Defense imaging applications are pushing as hard or harder than any commercial market. Higher resolution, faster frame rates, and the requirement for on-camera processing decisions before data ever reaches a downstream system — these aren't nice-to-haves in EO/IR targeting or airborne ISR. They’re requirements.

The data rate problem is where most architects first encounter the wall. CoaXPress and the newly released GigE Vision 3.0 standard both support aggregate throughput in the 40 Gb/s to 100 Gb/s range. Routing that data downstream to a CPU for processing isn’t a viable strategy in real-time applications; by the time a frame is buffered, transferred across the interface, and queued for software processing, the moment the system was supposed to act on has passed. A 10-core i9 processor handling data from a 2,200+ fps camera runs out of headroom. The throughput simply exceeds what serial software execution can service.

The architectural answer is to move the processing into the camera. With an FPGA inside the imaging device, algorithms execute on the pixel stream as it comes off the sensor — before a full frame is assembled, before any data crosses an interface. Latency drops to microseconds. Closed-loop control at speeds no PC-based pipeline can match becomes possible. GPU-augmented architectures can close some of this gap in unconstrained environments, but they don’t survive the SWaP-C and environmental hardening requirements of most deployed defense platforms.

In-sensor processing also directly addresses image quality problems specific to defense applications. Flat field correction, temporal noise reduction, radiometric normalization, lens distortion correction, and image enhancement aren’t consumer refinements — in EO/IR targeting and airborne ISR, they determine whether a system reliably detects a target or generates false positives. In missile guidance, a noisy or geometrically distorted feed isn’t a degraded capability — it’s a failure mode.

Defense programs also operate beyond the visible spectrum. SWIR cameras — used for through-haze target acquisition and low-light sensing — represent a growing segment of military imaging, and custom sensor configurations are the norm rather than the exception in most programs.

Three deployment paths are available. Processing can happen within the camera itself at 40 Gb/s, using custom OEM implementations. It can happen in the frame grabber, effectively converting any existing camera into a customizable intelligent device. Or it can happen at the edge via AMD Embedded+ with a customizable I/O card, allowing a single embedded computer to manage multiple camera types and protocols simultaneously.

RFSoCs: direct RF sampling at the edge

Of the three technologies covered here, RFSoC is drawing the most concentrated attention from defense electronics programs right now — and for good reason. It eliminates an entire layer of the traditional RF signal chain.

Previous RF processing architectures placed a discrete ADC between the antenna and the FPGA. That component added board space, drew power, introduced latency, and created an analog-to-digital conversion bottleneck that constrained the bandwidth and dynamic range of the entire system. AMD’s Zynq RFSoC and Versal RFSoC families remove it. High-speed ADCs running at 4+ gigasamples per second and DACs at 6.5 gigasamples per second are integrated directly on the same die as the FPGA programmable logic and ARM CPU cores. The antenna now connects directly to a chip that samples, processes, and acts on the RF signal in hardware.

The practical demonstration of this capability is straightforward: sample a wideband RF signal, run an FFT to identify frequencies of interest, apply bandpass filters, extract and classify the signals — all executing in real time in FPGA hardware, with no software in the critical path. The data rate math explains why software can’t be in that path. Eight ADC channels at 4 gigasamples per second at 12-bit resolution generates 384 Gbps of raw data. No embedded CPU or GPU handles 384 Gbps. FPGA-based processing isn’t a design preference at that data rate — it’s a necessity.

Defense applications that benefit span multiple mission sets: drone detection and RF-based frequency classification, electronic warfare signal identification and countermeasure generation, unauthorized RF environment monitoring, wideband SIGINT, and radar signal processing. All of them run into the same bottleneck with discrete ADC architectures, and all benefit from the same solution.

The form factor story matters as much as the capability story. The Trenz RFSoC System-on-Module puts all of this capability into an embeddable module with 4 ARM cores running Linux, 4GB RAM, and PCIe or network connectivity — designed to disappear inside a custom enclosure. Defense programs that previously required custom board development to get RFSoC capability now have a production-ready starting point. VITA 49.2 waveform standard support, custom carrier board design, and algorithm porting to FPGA hardware are the remaining integration challenges — not the silicon.

One pipeline, three entry points

Whether the input is a photon, a pixel stream, or an RF signal, the engineering objective is the same: process it faster, closer to the source, in a smaller and lower-power package than the previous architecture required. SoC FPGAs, in-sensor camera processing, and RFSoC each address a different point in the sensing-to-action chain. Together, they represent a coherent architectural shift away from centralized, multi-board processing toward distributed intelligence at the point of capture.

AMD Embedded+ is the clearest current expression of where this convergence leads: a single board combining x86 software flexibility, FPGA hardware speed, and AI inference capability, adaptable to cameras, RF front ends, networking, or any combination of sensors a defense application requires. It doesn’t force a choice between software accessibility and hardware performance — it offers both on the same substrate.

The barrier to entry for this class of technology is lower than it has ever been. HLS tools that compile C/C++ directly to FPGA logic, production-ready SoMs in embeddable form factors, and experienced design partners mean defense contractors no longer need to build from first principles. The engineering investment required has dropped substantially from where it stood five years ago.

Concurrent EDA is an AMD Elite-certified FPGA design services firm and hardware distributor with over 20 years of experience in FPGA development for defense applications. Customers include the U.S. Navy, U.S. Army, DARPA, and major prime contractors. Concurrent EDA supports module distribution, custom FPGA design services, and algorithm development and porting across all three technology areas covered here — SoC FPGAs, high-speed camera systems, and RFSoC platforms.