HI-6300: MIL-STD-1553/1760 Protocol IP Core

May 2, 2022
MIL-STD-1553 / MIL-STD-1760 IP core solution providing a complete single or multi-function interface between a host processor and MIL-STD-1553B bus. Supports BC, MT or RT functions using a high-performance synchronous host interface and 64K ECC RAM.

The Holt MIL-STD-1553 / MIL-STD-1760 IP core solution provides a complete and compliant single or multifunction interface between a host processor and MIL-STD-1553B bus. The IP Core supports Bus Controller (BC), Monitor Terminal (MT) or Remote Terminal (RT) functions and is fully software compatible with Holt’s existing hardware solutions, MAMBATM or HI-6130, HI-6131 families.

All options have a high-performance synchronous host interface, allowing easy connection to AMBA AXI4 interface protocol or PCIExpress. Enabled terminals communicate with the MIL-STD-1553 buses through a shared dual bus transceiver, HI-1587, and external MIL-STD-1553 isolation transformer, also available from Holt. The HI-6300 is the only MIL-STD-1553 IP Core providing native Error Detection and Correction on the embedded 8K or 64K words of block RAM. The user-provided input clock is selectable from 50 or 100MHz. A comprehensive built-in self-test is also available and MIL-STD-1760 busy bit response time is supported with an external input signal.

The Holt Multi-Core IP product includes a Verilog IP core, test bench, and supporting documentation, allowing designers to instantiate the core in a variety of FPGA or ASIC implementations. Also available is a high-level API software library supporting Linux, VxWorks, or bare metal implementations. The API is compatible with competitor legacy APIs allowing developers to reuse existing application software. A developer’s kit (ADK-6300) using a Xilinx Zynq UltraScale+ MPSoC ZCU102 FPGA Evaluation Kit and including Holt API software is also available.


●     Software compatible with Holt’s existing hardware solutions: MAMBATM or HI-6130/31 families

●      BC/RT/MT or RT/MT variants

●      IP is based on fully validated IC solution

●      Available DO-254 Certification Package supporting Design Assurance Level A (DAL A)

●      Up to 64K words static RAM with RAM Error Detection/Correction and BIST

●      High-performance synchronous AXI4 host interface

●      API software library supporting Linux, VxWorks and bare metal

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