Digital Receiver

May 8, 2014
The digital receiver module has eight independent channels of digital down-convertor (DDC) and one FFT embedded in the Xilinx Virtex-6 FPGA. It allows users to record the data directly from the ADCs or down-convert the channels modulated on the IF band. The module can be plugged into the PCI Express slot in the Windows/Linux PC and record data using the example software. Each DDC has its own programmable tuner, low-pass filtering, gain control, and decimation setting, supporting eight independent output bandwidths up-to 50 MHz. The data is packetized in VITA 49 format with the accurate timestamps, synchronous to the external PPS signal through the Digital IO (DIO). The DDC channel can be enabled and disabled on the fly to save the storage and bandwidth to the host computer. The embedded power meter monitors the power (dBFS) of the ADC inputs, allowing users to perform possibly analog gain control in the external front-end device. The 32K points FFT core calculates the wide-band spectrum of the ADC data or the narrow-band spectrum of the DDC output data. The programmable threshold monitoring spectrum detects the activities up-to 512 bins. The development kit, which is consist of individual IP cores, is also available for the custom design. Users can insert the custom- made cores for more advanced applications. Download Data Sheets & Pricing Now!!!

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