Officials from Actel Corp. and Synplicity, both of Sunnyvale, Calif., together are developing a logic synthesis methodology in Synplify 3.0c that will enable field programmable gate array (FPGA) designers to meet the tight single-event upset requirements of new military, deep-space, planetary, and communications spacecraft. Actel makes rad-hard FPGAs, and Synplicity makes logic synthesis tools. The new version of Synplify is designed to work with Actel`s RH1280 RadHard device, RP1280A and RP13100 RAD-PAK devices, and RadTolerant A1280A and A14100A devices. It enables designers automatically to infer sequential elements such as C-C flip-flop macros and triple-modular redundancy macros to minimize single-event upset in rad-hard FPGAs. For more information, contact Actel`s Mike Sarpa by phone at 408-739-1010, or on the World Wide Web at http://www.actel.com/. - J.K.