Complex ICs at Fujitsu require advanced test techniques

Integrated circuits are becoming increasingly complex, and that poses problems for manufacturing and testing. To test a chip of as many as 10 million gates costs 10 cents a second on today`s automatic test equipment (ATE) says Sobhan Mukherji, manager of advanced technology at Fujitsu Semiconductor Group in San Jose, Calif.

Dec 1st, 1998
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Integrated circuits are becoming increasingly complex, and that poses problems for manufacturing and testing. To test a chip of as many as 10 million gates costs 10 cents a second on today`s automatic test equipment (ATE) says Sobhan Mukherji, manager of advanced technology at Fujitsu Semiconductor Group in San Jose, Calif.

Furthermore, the chips typically sell for $5 to $30 apiece. What is necessary, he maintains, is built-in self test, or BIST, techniques that can cut costs and reduce time-to-market.

Fujitsu officials turned to LogicVision Inc., also based in San Jose, to apply a BIST solution known as SOCKET for testing system-on-chip (SOC) devices (for more, see special report page 13). The basis of this technique is a reusable test methodology to create plug-and-play test and diagnostic capabilities. Fujitsu specialists are using this approach for their current devices, with 0.25- to 0.35-micron feature sizes. They will expand it to its 0.18 line next year.

These are relatively large digital signal processing chips for such hand-held applications as cell phones and video decoders, Mukherji notes. This approach was first applied to the company`s low-voltage devices. When fully implemented, is expected to chop 30 days off the usual 100-day turnaround time, he adds.

Kiminori Fujisaku, general manager of the group, stresses what he calls "the efficient and repeatable test methodology that we have been looking for to satisfy customers of our advanced SOC products." He adds, "By enabling an effective hierarchical SOC test process, Fujitsu Semiconductor Group can achieve faster time-to-market and more cost-effective manufacturing test."

Since announcing their SOCKET partner program in June 1997, LogicVision officials have worked with such customers as Fujitsu to confirm the SOC test solution. The Fujitsu SOC test chip, for example, combines multiple cores (including legacy cores) and embedded memories. The test chip requires a diverse set of test capa- bilities: embedded ATE for logic and memories, scan-based automatic test pattern generation, and functional test for legacy cores. - J.R.

For more information on the SOCKET test methodology, contact LogicVision by phone at 408-453-0146 or 888-584-2478, by fax at 408-467-1180, by e-mail at info@ logicvision.com, by post at 101 Metro Drive, Third Floor, San Jose, Calif. 95110, or on the World Wide Web at http://www. logicvision.com

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Fujitsu Semiconductor Group is using the SOCKET system-on-a-chip test system from LogicVision to reduce the load on test equipment for integrated circuits.

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