By André Stolmeijer and Rajiv Jain
Field-programmable gate-array (FPGA) technology has become popular among system designers for the design flexibility it offers. The amorphous-silicon-antifuse FPGA technology is particularly useful, offering a combination of high circuit density and low power consumption along with nonvolatile programming and high reliability.
To make the most of that reliability, FPGA vendors need to consider the antifuse’s wear-out mechanisms and mitigate them through a combination of design, testing, software tools, and programming control.
An amorphous-silicon antifuse at its most basic is a dielectric separating two electrodes, with amorphous silicon as the dielectric. The dielectric normally exhibits giga-ohm-level resistance, effectively isolating the electrodes. Upon application of a suitable programming voltage and current, however, a region of the amorphous silicon forms a conductive channel weaker than 100 ohms connecting the electrodes.
The programmed antifuse behaves as a stable, reliable, linear resistor within its operating range and should maintain its low resistance during the device’s lifetime. If damaged, however, the programmed antifuse adopts a nonlinear behavior and its resistance becomes unstable. The resistance of a damaged programmed antifuse can vary from a hundred to tens of thousands of ohms and can change substantially over time when significant current flows through it.
This instability could cause field failures if a deployed device contained damaged antifuses. If the antifuse is being used to tie a gate high or low, the damaged antifuse will still serve to hold its gates at the proper logic levels. The signal propagation and switching speed of a CMOS logic circuit, however, are functions of the line resistance and load capacitance. In a high-speed circuit, the damaged antifuse’s unstable resistance can create variations in circuit timing. The delay can change from nanoseconds to microseconds, leading to field failures that are difficult to diagnose.
Excessive operating current through the antifuse is the typical cause of damage. DC current density has an influence on the mean time to failure for programmed antifuses. The cross sectional area of the pathway is a function of the programming current and programming algorithm along with the height, width and polarity of the programming pulses, and is typically a hundred nanometers squared. As the DC data shows, increasing the current density through the programmed antifuse strongly accelerates the failures. This strong dependence also means that reducing the operating current can significantly increase the lifetime of the programmed antifuse.
Such DC currents do not often occur in the normal operation of an FPGA. Typically, the programmed antifuse in a design connects a CMOS driver circuit to a capacitive network. In this arrangement, only AC capacitive currents flow through the programmed antifuse. The peak AC current-a function of the switching frequency, load capacitance, antifuse resistance, and driver output-can stress the programmed antifuse and result in failure over time. The last graph below shows the number of clock cycles that the antifuse can handle before failure as a function of current density, showing the same strong dependence as for DC currents.
Controlling the operating conditions at the programmed antifuse is only one step that can be taken to make the most of device reliability. There are also factors during the logic design, design routing, antifuse program sequencing, and testing that can affect reliability. Proper care can reduce the likelihood of damaging a programmed antifuse.
The first step in reducing the likelihood of damaging a programmed antifuse involves design. During logic design, following a few simple rules can help ensure reliability by avoiding risky situations. To prevent inadvertent programming of antifuses during normal operation, for instance, no antifuse should be directly connected to any external signal or power bus. Noise on external signal or transients on the power and ground buses can create a high enough voltage across an unprogrammed antifuse to initiate programming.
Next, testing should screen 100 percent of the unprogrammed antifuses at the wafer level to ensure they will not program below a certain voltage, and that they will remain in their high resistance unprogrammed state.
A similar check at final test ensures that the unprogrammed antifuses were not damaged during packaging. The wafer level test and the final test should verify that the programming circuitry can pass the proper voltages and currents. A final check should be done on the programmer immediately prior to programming to ensure that antifuses did not become damaged after final test.
Design routing creates the final circuit networks, which in turn determine the effective downstream capacitance for each programmed antifuse.
Keeping that capacitance below a set threshold will limit the peak AC current through the programmed antifuse. Thus, design routing software can reduce the number of antifuses operating at high currents by limiting the downstream capacitance. The router can select less capacitive wire lengths for different speed applications, or buffer large networks to create smaller less capacitive networks. Lowering the number of antifuses operating at high currents increases the programmed part’s reliability.
An often-overlooked step is to control the order in which the antifuses get programmed. As the device is being programmed, networks form. Programming pulses applied to one network may capacitively program any antifuses connecting to another network. As a result, the antifuse can become damaged, creating a yield or even a reliability problem. Sequencer software should forbid these cases and finds an alternate sequence.
Finally, control of the programming current is critical for ensuring antifuse reliability.
André Stolmeijer and Rajiv Jain are both with the technology development department of Quick Logic Corp. in Sunnyvale, Calif.