Complex RF, mixed-signal ICs pose new test challenges
To cope with the highly integrated mixed-signal devices common in today`s communications systems, designers are turning to a new breed of tester
To cope with the highly integrated mixed-signal devices common in today`s communications systems, designers are turning to a new breed of tester
By John H. Mayer
Test engineers in military, aerospace, and commercial industries are facing an entirely different communications landscape today from what they faced only a few years ago. The rapid evolution of new wireless technologies such as spread-spectrum battlefield communications, satellite-based navigation, wireless personal communications, and networking technologies has given users unprecedented access to data and voice messaging.
But with these advancements have come several new test challenges. For just as wireless technology has matured over the last few years, so too have the microwave/ RF devices that sit at their cores.
Not long ago the typical RF front-end device might have combined one or two functions in a simple 8-or 16-pin package. Today it is not unusual for systems to feature RF components that integrate a wide range of building blocks including low-noise amplifiers (LNAs), mixers, voltage-controlled oscillators, synthesizers, modulators, and demodulators in a single 64-pin part.
"In the early 1990s, RF devices offered relatively limited functionality, perhaps combining a mixer and an LNA in a single package," observes Ken Donovan, wireless/RF market manager for test equipment manufacturer LTX Corp. in Westwood, Mass. "The devices we`re seeing today typically use a BiCMOS process to integrate into a single chip what was just a few years ago delegated to separate RF building blocks."
Typical examples of this evolution are single-chip transceivers for applications like global systems for mobile communications. Devices like Lucent Technology`s 2020 transceiver combine two fixed-frequency synthesizers, a digitally programmable frequency UHF synthesizer, and other functions in a 64-pin package. Other dual-mode devices support several wireless standards, such as FM and code division multiple access, requiring testers capable of supporting different modulation schemes.
"These new devices require more flexibility than a traditional RF test system," notes Donovan. "Test systems must support high-pin-count packages that contain modulators, demodulators, filters, and A-D and D-A converters. That requires true mixed-signal test capability with a seamless integration of intelligent digital, DSP, and RF systems."
The key to seamless integration is tight synchronization across the mixed-signal test system. Precise control of timing between analog and digital events is crucial to achieving accurate, repeatable tests. Testers must generate analog waveforms at the precise moment, define the precise start of analog measurements, and then lock analog waveforms to digital events.
Like many mixed-signal test systems today, The Synchro II Series from LTX, used by Lucent, Qualcomm Inc. of San Diego, and other communications systems manufacturers, are digital signal processor (DSP)-based and use a common clock reference across the RF subsystem, the digital subsystem, and standalone instruments. "Basing it on one common reference gives you the coherency that you need as you go to higher and higher levels of integration and ensures the accuracy and repeatability that test engineers are used to," Donovan says.
Similarly, the A5 family of mixed-signal testers from Teradyne in Boston uses a reference clock that provides four independent clock sources. Any clock source is available to any AC instrument within the test system. The subsystem generates a very low-jitter clock that is programmable over the 160-to-200 MHz range with 4 Hz resolution.
The Teradyne system uses a mixed-signal microcode control technique called vector locking to ensure test repeatability. The system assigns microcode commands that control the analog instruments to each digital vector in a sequence at the same time as digital events are defined and programmed.
Synchronization comes by delivering mixed-signal (analog) microcode to the AC instruments to control waveform generation and capture at the exact same time as digital events move to digital formatting and timing systems.
Teradyne`s A567 mixed-signal test systems feature a dual mixed-signal test head and AC and DC instrumentation to increase parallel test capabilities. Among Teradyne`s customers is Harris Semiconductor of Melbourne, Fla., a manufacturer of ICs for military and commercial applications. "The A567`s parallel test capability provides the right economics and its compatibility with earlier A575/A585 production test systems gives us the flexibility to respond to rapidly evolving device requirements," notes Joe Boarman, director of product and test engineering at Harris Semiconductor.
Analog and digital synchronization on the ITS 9000EXA, the new mixed-signal tester from Schlumberger of San Jose, Calif., is accomplished at two levels. One level allows synchronization of the digital master clock and the analog clock to ensure that the most appropriate sampling rate can be selected and is not dependent on the digital rate.
A second level uses an event bus that is controlled from the digital pattern. This two-level architecture enables designers to test complex scenarios such as starting the measure when a certain digital pattern appears. The 100/200 MHz tester can be configured with as many as 448 digital pins and four analog channels. Early users of the system include SGS-Thomson Microelectronics of Agrate, Italy, and United Microelectronics Corp. of Taiwan.
Tester flexibility is a growing concern for designers of wireless and microwave systems, particularly as they integrate new, high-performance communications ICs. A growing number of design teams need test systems that offer versatile RF switching, broad frequency coverage and high power capability. Most automatic test equipment vendors are attempting to fill this evolving requirement by building modular systems that leave their customers the opportunity upgrade quickly as requirements change.
Teradyne`s A5 family, for example, comes in a variety of configurations for specific applications. And microwave options add 3 GHz vector network analysis and 6 GHz scalar measurement.
To extend test coverage out to 3 GHz, LTX experts recently developed a new module called the Personal Communications Systems Family Board (PCS FB). Designed for the RF02 option to the Synchro test system, the PCS FB gives the user eight bi-directional RF ports with S parameter measurement capability as well as the ability to perform all scalar source type of measurements. The board also supports third order intercept, isolation, phase noise, return loss, and other typical RF tests.
The system is built around eight port modules, each of which features a directional coupler for vector measurements as well as level ranging circuitry. Output modules house a combiner that allows RF signals to be summed for intermod tests. Each input module`s auxiliary and cross couple mode provides flexible RF signal distribution. To make the most of performance and reliability, the PCS FB uses solid-state gallium arsenide FET switches instead of traditional mechanical switches.
To simplify installation and removable of the device-under-test (DUT) board in production environments, the PCS FB`s top assembly consists of a collapsible collar, lock down ring, and DUT board. The DUT board fits into a "mayonnaise-jar" style lid that locks down with a two-thirds turn of an outer lock down ring. Mechanical springs in the top assembly simplify docking to probes and handlers.
A crucial factor in the development of accurate RF test results is minimizing the path from a device`s pins to the tester`s RF ports. To ensure the shortest path, the PCS family board`s eight RF ports are located radially around the DUT. "It basically takes all of the RF signals off the eight ports and allows the user to multiplex them around, but the nice thing is that the RF ports are less than 2 inches away from the device pins," notes Donovan.
While today`s highly integrated mixed-signal devices demand high performance testers, the economic demands of today`s markets, including the military, make it increasingly difficult to justify million-dollar-plus testers. In fact, test strategy has quickly become a critical competitive strategy in many IC manufacturer`s business plans.
Case in point is mixed-signal IC maker Crystal Semiconductor of Austin, Texas. A subsidiary of Cirrus Logic Inc. of San Jose, Calif, Crystal Semiconductor has grown rapidly over the past five years as its leaders have expanded the number and complexity of the products they manufacture. Today company engineers build a wide range of high-resolution data converters, digital audio and data communications ICs.
While Crystal officials at one time used their own internally-developed testers, increasing device complexity and the expanding diversity of their product line suggested a more efficient, cost-effective approach to test. Developing custom test solutions for a growing array of new products was not cost-efficient, and as the IC maker entered new markets, test costs played a larger role in winning new customers. "In new markets, low production and test costs are critical to encourage high adoption rates and to optimize profit margins," notes Executive Vice President Michael J. Callahan Jr.
To meet their diverse needs, Crystal designers chose the HP 9490 mixed- signal test systems from Hewlett-Packard Co. of Palo Alto, Calif. The HP 9490 features as many as 256 digital pins and recently added an RF option that adds eight independent RF ports capable of sourcing as much as 3 GHz and a measurement range of 6 GHz. With the 9490`s modular architecture, engineers at Crystal along with Hewlett-Packard`s support team were able to develop solutions specifically designed for specific markets. In addition, Crystal and HP engineers developed several unique test applications for rapid start-up on many of the company`s various device types. One real-time DSP program managed to reduce test time on one particular device by more than 40 percent.
More recently, HP officials have attempted to address the cost concerns of IC manufacturers with a new line of cost-effective mixed-signal testers, the HP 94000 series. Introduced within the last year, the new family of mixed-signal IC testers makes liberal use of highly integrated ASICs, improved manufacturing processes, and low system hardware overhead. Despite its lower cost, however, the new family of testers offers fast digital performance, a low-noise floor, and all the analog instrumentation necessary for efficient testing of state-of-the-art devices.
Moreover, HP engineers have designed the 94000 series to be completely compatible with the 9490 series testers, to free users from modifying DUT boards and test program software. Flexible configurations let test engineers tailor the system to meet different technical and budget constraints.
All models in the 94000 family offer faster edge slew rates than the 9490 series, providing sharper digital waveforms. To make the most of timing flexibility and ease of programming, the testers feature 16 formats and 16 timing sets on the fly on a per-pin basis.
On the analog side, the system features 40 MHz, 12-bit digitizer with a bandwidth of 80 MHz and a 1 GHz 8-bit arbitrary waveform/generator. It includes the same RF capability as the RF9490, including 8 RF ports capable of sourcing as much as 3 GHz and measuring up to 6 GHz. The RF hardware is capable of making spectral, vector, modulation/ de-modulation and noise-figure measurements.
Other ATE vendors are also focusing on driving down the cost of test. Making extensive use of CMOS technology, test system developers at Advantest in Tokyo built the "down-sized" T7323 Mixed Signal Test System at 30 percent lower cost, while reducing tester footprint by 40 percent. The 128-pin 20/40 MHz tester uses a DSP architecture that runs at 133 million floating point operations per second.
To meet the limitations of escalating capital costs, ATE vendor TMT Inc. in Sunnyvale, Calif., introduced last year the ASL-1000. The 20 MHz tester uses an innovative "no relay matrix" design that features a parallel instrument capability where the number of voltage/current instrument resources is limited only by the size of the device under test. Company officials claim the tester can cut the cost-per-test by 50 percent and increase throughput on test of low-cost mixed signal devices by as much as 250 percent.
Of all the challenges mixed-signal ATE vendors face today, perhaps the most daunting is calibration. As devices move up to higher frequencies, everything from the socket and the fixturing to the probe card or DUT interface board can skew the final measurement. Traditionally test engineers have calibrated for these effects in their instrumentation by plugging standards into their bench vector network analyzer. But undocking a tester and calibrating it manually is hardly conducive to efficient and cost-effective production test.
Some ATE vendors have tried to minimize downtime by integrating instrument standards directly into their architecture. In effect each instrument has an internal standard built in. In Teradyne`s systems, for example, the tester will periodically signal to the handler or the prober to wait for a couple of minutes while it goes off and calibrates automatically. In effect, the system maintains calibration without the user having to lift a finger. A critical element to a calibration scheme of this nature is excellent RF connector repeatability.
While these autocalibration approaches calibrate microwave instruments up to a plane where that signal ends, they still do not compensate for the effects on the signal path up all the way through the DUT interface board to the device.
To compensate for loss through the test head hardware, ATE vendors use de-embedding techniques that, through mathematical simulation using a program such as Spice, define the error between where the signal can be calibrated and its final destination. The longer the transmission line, the more de-embedding is required. The final value is then inserted into the test program and included every time the point is calibrated.
Used in wafer sort, final test, and device characterization, LTX`s Synchro II mixed-signal tester is designed to handle many of the more complex, highly integrated RF/wireless ICs being developed today.
Designed to test communications ICs out to 3 GHz, LTX`s PCS family board is divided into three primary blocks: port modules, RF output modules and RF input modules. Each of eight port modules, combines a directional coupler for vector measurements and level ranging circuitry.
The new HP 94000 series tester is designed to meet the performance requirements of the most complex mixed-signal ICs at a cost significantly lower than its predecessors. The product line supports data rates as fast as 533 megabits per second.
COTS solution tackles mixed-signal test on B-2
Mixed-signal test presents many of the same challenges at the assembly level as it does at the IC level. One of the first mixed-signal ATE systems delivered to the U.S. Air Force under the COTS initiative is a test systems developed for the B-2 bomber depot at Tinker Air Force Base, Okla.
Since the early 1980s, Air Force officials have purchased modular automatic test equipment to serve their depot test needs. Determined to cut costs and development time with a COTS approach, leaders from the U.S. Department of Defense and from prime contractor Northrop Grumman Corp. turned to Teradyne in Boston and to Hewlett-Packard Co. of Palo Alto, Calif., to come up with a solution for the B-2 stealth bomber. The overall objective was to combine COTS components with the depot`s system-level performance requirements.
With more than 800 different types of printed circuit boards, each with complex analog, digital, and RF circuitry, the B-2 test requirements were nothing less than demanding. Any system devised for the program had to support digital clock and data rates as fast as 80 MHz, offer accurate analog stimulus and measurement, and support RF source and measurement up to 20 GHz.
The solution that engineers from Teradyne and Hewlett-Packard devised was an amalgam of different vendors` products. The complete ATE system that was finally delivered to the depot included 11 digital/fast analog (DIFA) test stations, six radio frequency analog/ digital (RFAD) test stations and 18 program development stations (PDSs) including more than 100 workstations for off-line TPS development.
Indicative of the wide range of third-party products in the system was the suite of digital/analog/RF TPS development tools integrated into the PDS. The tool set included the Falcon Framework and Design Architect from Mentor Graphics in Beaverton, Ore., the LASAR digital simulations software from Teradyne, the Saber analog simulation software from Analogy of Beaverton, Ore., Libra/Omnisys RF simulations software from HP-EEsof, and VEE analog/RF test development software from Hewlett-Packard.
To meet the high data rates of the B-2 subsystems, team members based the digital subsystem of the DIFA on Teradyne`s L393 test system. Capable of supporting 80 MHz data rates, the L393 offers 528 bi-directional channels. The analog functions in the DIFA came from 34 IEEE and VXI instruments sourced from a variety of vendors.
An analog matrix, along with switching relays on the L393`s channel cards, provides hybrid capability on 400 of the digital channels to simplify test program coding. "The DIFA has to be capable of testing every function on the B-2, from simple fuel level indicators to complex radar signal processors," says Dave Menzer, HP`s field program manager for the B-2 ATE project. "Our primary objective in working with third-party analog instrument suppliers was to ensure that all of the instruments presented a seamless look-and-feel to the TPS developer."
The B-2 RFAD test station builds on the DIFA design by adding a 32- instrument RF subsystem. In the RFAD, controlling the L393-based digital test system is an Alpha-Station from Digital Equipment Corp. in Maynard, Mass., while managing the analog and RF subsystems are a Sun Microsystems SPARCstation, which communicates to the AlphaStation over an Ethernet link.
One of the biggest challenges for designers of the RFAD`s RF subsystem was minimizing signal degradation through cabling. "The driving issue in the design was to ensure the integrity of RF signals at the tester interface," notes Mike Moorehead, HP`s lead engineer on the project.
Key to achieving that goal was a complex RF switch matrix that`s designed to extend specifications to the RF interface. The matrix helped ensure proper power levels and pulse measurements. But calibration and normalization routines, which are capable of learning the losses inherent in each connection path and then controlling the application of correction factors to stimulus and measurement values, also played a significant role in maintaining signal integrity.
Another key challenge came with design of the RFAD "bridge," an interface between the RF subsystems and the L393 DIFA. Designers had to minimize the distance signals travel to the RF interface while at the same time carefully planning for adequate airflow and heat dissipation. "It was probably the largest mechanical challenge we faced on the B-2 project," notes Chuck Schwarz, Teradyne`s B-2 program manager.
Of course, on any test system of this complexity, ease-of-operation was identified early on as a key factor in the efficiency of B-2 depot personnel. Rather than force operators to learn and use software from two different vendors, the DIFA and RFAD test stations share a common programming and test executive environment that combines the capabilities of Teradyne`s ProgramGuide software and Hewlett-Packard`s VEE.
All TPS development tasks, from test programming to tester operation, run from a single graphic user interface. That collaboration between Teradyne and Hewlett-Packard engineers should pay off many times over for B-2 personnel during the planned 20-year lifecycle of the test system. -J.M.
One of the more difficult problems designers of the B-2 Depot ATE system faced was building a bridge interface on the RFAD that integrated the RF subsystem with the digital and analog subsystems without compromising signal integrity.