Grandis wins DARPA contract by Department of Defense to develop Spin-Transfer Torque Random Access Memory

MILPITAS, Calif., 21 June 2010. Grandis Inc. won $8.6 million from the Defense Advanced Research Projects Agency (DARPA) for the second phase of a research project developing spin-transfer torque random access memory (STT-RAM) chips. STT-RAM is a next-generation, solid-state memory technology that is dense, fast, non-volatile, and radiation-hard, making it well suited for defense applications.

Posted by Courtney E. Howard

MILPITAS, Calif., 21 June 2010. Grandis Inc. won $8.6 million from the Defense Advanced Research Projects Agency (DARPA) for the second phase of a research project developing spin-transfer torque random access memory (STT-RAM) chips. STT-RAM is a next-generation, solid-state memory technology that is dense, fast, non-volatile, and radiation-hard, making it well suited for defense applications.

The first phase, supported by an award amount of $6.0 million, began in October of 2008 and was scheduled to last two years.

The program is being carried out by a collaboration between Grandis, the Universities of Virginia and Alabama, and the College of William and Mary. Additional support has been provided by the National Institute of Standards and Technology and the Naval Research Laboratory.

Under the direction of Principal Investigator Dr. Eugene Chen of Grandis, development work has covered STT-RAM materials and processes, as well as STT-RAM architecture and circuit blocks. During Phase II, work will ultimately include test and verification of STT-RAM integrated memory arrays.

"The success of this DARPA program is dependent on this exceptional and well-knit team consisting of industry and university partners," according to the DARPA/MTO program manager for the STT-RAM program, Dr. Dev Shenoy.

"STT-RAM has huge potential as the only non-volatile Random Access memory which scales beyond 10nm. It is also the only technology fast enough to replace the existing DRAMs. It can replace embedded SRAM and flash at 45-nm, DRAM at 32-nm, and ultimately can replace NAND,'' says Farhad Tabrizi, CEO and president of Grandis.

Dr. Eugene Chen, Principal Investigator for the project, explains: "Approval of funding for the second phase of this project required reaching stringent goals for Phase I, a milestone we reached in March of this year, over six months ahead of schedule. These goals included demonstrating STT-RAM write energy of less than 0.25 pJ, read and write speeds of 5 nanoseconds and thermal stability greater than 60 kT, all on the same bits, plus projected endurance of greater than 1E16 cycles. In fact, we demonstrated these challenging metrics not just at 5 ns but also over a wide range of write speeds from 1 ns to 20 ns."

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