DARPA eyes microelectronics optical interconnects for high-performance embedded computing boards

ARLINGTON, Va. – U.S. military researchers are asking the microelectronics industry to find ways of using optical interconnects on high-performance embedded computing boards to enhance bandwidth, power efficiency, channel density, and link reach.

DARPA eyes microelectronics optical interconnects for high-performance embedded computing boards
DARPA eyes microelectronics optical interconnects for high-performance embedded computing boards
ARLINGTON, Va. – U.S. military researchers are asking the microelectronics industry to find ways of using optical interconnects on high-performance embedded computing boards to enhance bandwidth, power efficiency, channel density, and link reach.

Officials of the U.S. Defense Advanced Research Projects Agency (DARPA) have released a broad agency announcement for the Photonics in the Package for Extreme Scalability (PIPES) program.

PIPES seeks to enable disruptive system scalability by developing optical signaling technologies for digital microelectronics. The program will employ intimate integration of photonics with advanced integrated circuits to yield unprecedented system connectivity.

The project seeks to integrate photonic interconnects on state-of-the-art multichip modules for system prototyping; advance embedded optical signaling performance with emerging component technologies, photonic-electronic integration techniques, scalable architectures, and multiplexing concepts; develop low-loss optical packaging and reconfigurable switching technologies; and, establish a domestic ecosystem that gives military systems designers access to new capabilities for in-package photonic signaling.

Since the end of clock frequency scaling in the mid-2000s, the microelectronics industry progressively has embraced parallelism to sustain performance growth, DARPA researchers explain. Constraining the benefits of parallelism, however, is not computation at individual nodes, but by data movement between embedded computing nodes.

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While short-reach connects is possible today between on-chip cores and within multi-chip modules using high-bandwidth electrical links, this interconnect performance rapidly degrades at the longer lengths of circuit boards and beyond because of unfavorable scaling with frequency and reach. This restricts off-chip I/O capacity, reduces system performance, and limits scalability.

Granted, photonic transceiver modules can enable optical signaling with high bandwidth and minimal loss over long distances with optical fiber, yet optical I/O typically comes in pluggable modules on circuit boards, connected to MCM packages with electrical links whose power dissipation and density limit overall performance.

Instead, DARPA researchers are trying to find improvements by reducing signaling energy and latency, while increasing overall signaling capacity and component density. This is where the PIPES project comes in.

Developing efficient, high-bandwidth, package-level photonic signaling should have substantial influence on high-performance computing, on big-data applications that use machine learning, advanced sensors, and wireless interfaces.

While optical signaling is common today in such systems at the board and rack levels, it has not yet been integrated within component switch chips, central processing units (CPUs), and graphical processing units (GPUs).

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The PIPES program revolves around three technical areas: photonically enabled multichip modules; photonics for massive parallelism; and interconnect fabrics to facilitate package-level photonic I/O in future systems.

PIPES is a 42-month program divided into three phases: demonstration of concepts, components, and function; integration and prototyping; and establishing scalability, complexity, and maturity.

Companies interested should upload abstracts to the DARPA BAA Website no later than 20 Nov. 2018 at https://baa.darpa.mil, and full proposals no later than 17 Jan. 2019 online at www.grants.gov/applicants/apply-for-grants.html.

Email questions or concerns to Gordon Keeler, the PIPES program manager, at HR001119S0004@darpa.mil.

More information is online at https://www.fbo.gov/spg/ODA/DARPA/CMO/HR001119S0004/listing.html.

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