SAN JOSE, Calif., 27 Nov. 2013. Cadence Design Systems Inc. (NASDAQ:CDNS) announced its Front-End Design (FED) Summit, a day-long event on incorporating knowledge of physically aware design early in the front-end design implementation flow to save design closure time and boost performance.
The event will be held Thursday, 5 Dec. 2013 at Cadence Design Systems, Building 10 Auditorium, 2655 Seely Ave., San Jose, CA 95134.
FED summit attendees will network with fellow logic designers and speak directly with Cadence R&D staff about Encounter RTL Compiler, Encounter Test, and Conformal applications. According to a spokesperson, attendees at the day-long technical event will:
Hear from design teams about the challenges they faced during logic synthesis, advanced low-power design and verification, engineering change order (ECO), and design-for-test (DFT) implementation, and the strategies they employed to address them
Discover how best to achieve power, performance, and area goals on industry-leading IP cores
Network, share your knowledge, and exchange best practices with your industry peers
Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems.
